The Intel open source site, 01.org, hosts the Linux Kernel Perf project, and they have a 0-Day project.
[…] The infrastructure we developed to test the Linux kernel is called 0-Day. It is a service and test framework for automated regression-testing that intercepts kernel development at its earliest stages, and is available to the worldwide Linux kernel community. This project provides a further “shift-left” by testing key developers’ trees before patches move forward in the development process. Some key features of 0-Day are:
* Provides 1-hour response time around the clock, hence the 0-Day name.
* Performs patch-by-patch tests
* Covers all branches of a developer’s tree
* Performs kernel build and static semantics-level testing using industry static source code analyzers
* Performs boot tests, functional and performance tests on a variety of IA-based platforms in our labs
* Bisects code automatically when tests fail, or when performance regresses, enabling us to identify which patch caused the failure.
I just learned about this, and don’t know much about it yet, It sounds interesting, “performs boot tests”. Maybe it is the Intel version of ARM/Linaro’s LAVA?
It is sometimes funny to watch a company do open source. Intel’s 01.org, for Open Source projects, has a mailing list server with multiple lists:
There are lists for LUV and CHIPSEC. These work fine!
There is a list for Thunderbolt Software. …but it is a closed list, with no public archives. 😦
The text that it is a closed list:
“This is a hidden list, which means that the list of members is available only to the list administrator.”
There’s a list for Intel Kernel Guard Technology (KGT). It also is a closed list, with the same text as the Thunderbolt list. BUT, their archives are publicly-available.
There’s a list for BIOS Implementation Test Suite (BITS)!
But there are no archives, perhaps a closed list, or just broken archives?
I rather wish Intel used intel.com or 01.com for closed lists, and kept the Open Source-centric 01.0rg’s list all public, with working archives. 😦
I was just looking on Intel’s 01.org to see what’s new, or some older things I’ve not yet noticed.
I just noticed there are two projects with updated TPM 2.0 support:
TPM (Trusted Platform Module) 2.0 Software Stack (TSS). This stack consists of the following layers from top to bottom:
* Feature API (FAPI), see specification 0.12, (published but still in progress and unimplemented)
* Enhanced System API (ESAPI), (specification in progress and unimplemented)
* System API (SAPI), see 1.0 specification, (public, 0.97 implementation complete)
* TPM Command Transmission Interface (TCTI), used by SAPI to communicate with next lower layer (either the TAB/RM or TPM 2.0 device driver), see SAPI specification
* Trusted Access Broker/Resource Manager (TAB/RM), see 0.91 specification, (public, implementation complete)
This site contains the code for the TPM (Trusted Platform Module) 2.0 tools based on TPM2.0-TSS. Below is the name list of the implemented tools:
Subset 1: NV tools: tpm2_nvdefine tpm2_nvrelease tpm2_nvread tpm2_nvwrite tpm2_nvlist
Subset 2: Attestation tools: tpm2_takeownership tpm2_getpubek tpm2_getpubak tpm2_akparse tpm2_makecredential tpm2_activatecredential tpm2_listpcrs tpm2_quote
Subset 3: Key management tools: tpm2_createprimary tpm2_create tpm2_evictcontrol tpm2_load tpm2_loadexternal
Subset 4: Encryption tools: tpm2_encryptdecrypt tpm2_rsaencrypt tpm2_rsadecrypt tpm2_unseal
Subset 5: Signing tools: tpm2_sign tpm2_verifysignature tpm2_certify
Subset 6: utilities: tpm2_getrandom tpm2_hash tpm2_hmac tpm2_readpublic
The CHIPSEC team at Intel Advanced Threat Research (ATR) have setup a mailing list for public discussions on CHIPSEC!
Formerly, there was no list, and the only way to talk about CHIPSEC was to email email@example.com. Now we have a place for security researchers to talk about using CHIPSEC, and open source developers to talk about contributing patches to CHIPSEC.