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RISC-V-based Arduino

In their quest to democratize access to custom silicon, SiFive has announced the very first RISC-V-based Arduino just hours before the start of Maker Faire Bay Area 2017.

https://blog.hackster.io/sifive-unveils-the-first-risc-v-based-arduino-a4d07fe7f21f

 

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SiFive Coreplex IP for RISC-V

RISC-V is a free and open instruction set architecture based on modern design techniques and decades of computer architecture research. With over 60 member companies and a robust software ecosystem, RISC-V is set to be the standard architecture in all modern computing devices, from 32-bit embedded microcontrollers to 64-bit application processors and datacenter accelerators and beyond. SiFive Coreplex IP are the most widely deployed RISC-V cores in the world and are the lowest risk, easiest path to RISC-V. SiFive Coreplex IP are fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.

https://www.sifive.com/products/coreplex-risc-v-ip/

 

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RISC-V edition of Computer Organization and Design

Computer Organization and Design RISC-V Edition
1st Edition
The Hardware Software Interface
Authors: David Patterson John Hennessy
Paperback ISBN: 9780128122754
Imprint: Morgan Kaufmann
Published Date: 13th April 2017
Page Count: 696

https://www.elsevier.com/books/computer-organization-and-design-risc-v-edition/patterson/978-0-12-812275-4
https://www.elsevier.com/books-and-journals/book-companion/9780128122754
https://textbooks.elsevier.com/web/product_details.aspx?isbn=9780128122754
https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128122757

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6th RISC-V Workshop: call for papers

Registration and the call for presentations / posters is open for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be a four day event broken down as follows[…]

https://riscv.org/2017/03/6th-risc-v-workshop-registration-and-call-for-papers/

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Another RISC-V project

The other week I pointed out a RISC-V project on CrowdSupply:

https://firmwaresecurity.com/2016/11/23/onchip-has-risc-v-on-crowdsupply/

There’s another one, as Jeremy Bennett Embecosm announced on the Open Source Hardware User Group list:

Another RISC-V project

Hot on the heels OnChip and Open-V of comes

  https://www.crowdsupply.com/sifive/hifive1

I note they have already met their target on the first day (it wasn’t a very hard target).

More info:
http://oshug.org/cgi-bin/mailman/listinfo/oshug

https://github.com/sifive/freedom

https://www.sifive.com/

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SiFive: new RISC-V-based startup

Rick of EE Times has an article on a new hardware startup using RISC-V (as well as more info on recent RISC-V workshop):

http://www.eetimes.com/document.asp?doc_id=1330086&_mc=sm_eet_editor_rickmerritt
https://www.sifive.com/about/mission/

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