Registration and the call for presentations / posters is open for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017. As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be a four day event broken down as follows[…]
The other week I pointed out a RISC-V project on CrowdSupply:
There’s another one, as Jeremy Bennett Embecosm announced on the Open Source Hardware User Group list:
Another RISC-V project
Hot on the heels OnChip and Open-V of comes
I note they have already met their target on the first day (it wasn’t a very hard target).
Andrew Back posted a message on the Open Source Hardware list, noting that OnChip has a RISC-V chip on CrowdSupply.
“The fully open source RISC-V based 32-bit microcontroller, Open-V, is now crowdfunding on Crowd Supply:
Rick of EE Times has an article on a new hardware startup using RISC-V (as well as more info on recent RISC-V workshop):
Wow, the coreboot blog is busy, a lot of GSoC activity to catch up to!
Jneuschaefer is doing RISC-V updates to coreboot….
[GSoC] Better RISC-V support, week #2
[GSoC] Better RISC-V support, week #3
Hatim Kanchwala is working on FlashROM…
[GSoC] Multiple status register support, week #1 and #2
Antonello Dettori is working on SerialICE:
[GSOC] Panic Room, week #2
The last two blog posts on the coreboot blog are by two students working on their Google Summer of Code (GSoC) project. Both sound very interesting.
Jonathan Neuschäfer is improving coreboot’s support for RISC-V platforms, which was initially added in 2014.
Antonello Dettori is working on improving SerialICE, “which is one of the main tools used in reverse engineering an OEM BIOS”, including coreboot integration.
There’ve been a few presentations on porting UEFI to the RISC-V, but now there is public code! Abner Chang of HPE has submitted multiple patches with RISC-V support for various components of EDK-II.
[PATCH 0/3] *** EDK2 base tools support RISC-V processor***
EDK2 base tools support RISC-V arch. EDK2 build tool changes to generate RISC-V PE/Coff image from RISC-V ELF file, handle RISC-V relocations and generate EDK2 FW with RISC-V image machine type.
BaseTools: Support build RISC-V PE/Coff image.
The changes on BaseTools is for building RISC-V ELF image and PE/Coff Image. Also to generate FW and FV for RISC-V arch.
[PATCH 0/2] *** EDK2 MDE for RISC-V processor ***
MdePkg: MDE implementations for RISC-V arch. The implementations of RISC-V MDE base libraries.
Add RISC-V architecture image file machine code.
Add RISC-V architecture relocation type.
Add RISC-V architecture context buffer.
Add RISC-V architecture exception types.
Add RISC-V architecture PXE tag definition.
Add RISC-V architecture EFI image machine type.
Add RISC-V architecture removable media boot path.
Add RISC-V architecture processor binding.
[PATCH] OvmfPkg/PciHostBridgeDxe: [RISC-V] Add back OVMF PciHostBridge module.
Use OVMF PCI host bridge driver as the RISC-V platform BUS.
This driver is used by RISC-V Virtualization package (RiscVVirtPkg).
Currently the platfrom spec for RISC-V is not yet ready, thus we use PCI host bridge in temporarily.
[PATCH] RiscVVirtPkg: RISC-V QEMU package.
This is RISC-V QEMU package. The image which built from this package can be launched on QEMU RISC-V port (not official QEMU). RiscVVirtPkg utilizes below modules from EDK2 OVMF package,
– PciHostBridge DXE driver.
Use PCI host bridge driver as RISC-V platform bus spec for adopting PC/AT components.
QEMU firmware configuration.
– OVMF ACPI timer lib.
[PATCH] RiscVPkg: RISC-V processor package.
New processor package added to EDK2 open source for RISC-V.
[PATCH] MdeModulePkg/DxeIplPeim: RISC-V arch DxeIpl.
The implementation of RISC-V DxeIpl.
This is only the first round of these multiple patches, given initial discussion it is likely there will be another round. In the discussion for this patch, it appears there is more support upcoming, not yet public. In the thread, Abner mentioned:
“The UEFI/PI ECR for RISC-V is ready but not yet send to UEFI for review. I have been told to upstream RISC-V code first and then submit the spec. I will confirm this again.”
I am looking forward to seeing what happens with the RISC-V UEFI port, and seeing some consumer devices based on RISC-V!
For more info, see the various threads on the EDK2-devel list: