Call for Papers: 7th RISC-V Workshop

7th RISC-V Workshop November 28-30, 2017

We’re seeking proposals for talks and poster presentations conveying recent activity in the RISC-V community at the upcoming 7th RISC-V workshop hosted by Western Digital in Milpitas California on November 28-30, 2017.[…]

SiFive Coreplex IP for RISC-V

RISC-V is a free and open instruction set architecture based on modern design techniques and decades of computer architecture research. With over 60 member companies and a robust software ecosystem, RISC-V is set to be the standard architecture in all modern computing devices, from 32-bit embedded microcontrollers to 64-bit application processors and datacenter accelerators and beyond. SiFive Coreplex IP are the most widely deployed RISC-V cores in the world and are the lowest risk, easiest path to RISC-V. SiFive Coreplex IP are fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.


RISC-V edition of Computer Organization and Design

Computer Organization and Design RISC-V Edition
1st Edition
The Hardware Software Interface
Authors: David Patterson John Hennessy
Paperback ISBN: 9780128122754
Imprint: Morgan Kaufmann
Published Date: 13th April 2017
Page Count: 696

6th RISC-V Workshop: call for papers

Registration and the call for presentations / posters is open for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be a four day event broken down as follows[…]

Another RISC-V project

The other week I pointed out a RISC-V project on CrowdSupply:

There’s another one, as Jeremy Bennett Embecosm announced on the Open Source Hardware User Group list:

Another RISC-V project

Hot on the heels OnChip and Open-V of comes

I note they have already met their target on the first day (it wasn’t a very hard target).

More info:

coreboot GSoC updates (RISC-V, FlashROM, SerialICE)

Wow, the coreboot blog is busy, a lot of GSoC activity to catch up to!

Jneuschaefer is doing RISC-V updates to coreboot….

[GSoC] Better RISC-V support, week #2

[GSoC] Better RISC-V support, week #3

Hatim Kanchwala is working on FlashROM…

[GSoC] Multiple status register support, week #1 and #2

Antonello Dettori is working on SerialICE:

[GSOC] Panic Room, week #2

coreboot GSoC update: RISC-V and SerialICE

The last two blog posts on the coreboot blog are by two students working on their Google Summer of Code (GSoC) project. Both sound very interesting.

Jonathan Neuschäfer is improving coreboot’s support for RISC-V platforms, which was initially added in 2014.

Antonello Dettori is working on improving SerialICE, “which is one of the main tools used in reverse engineering an OEM BIOS”, including coreboot integration.

More information:

UEFI ported to RISC-V!

There’ve been a few presentations on porting UEFI to the RISC-V, but now there is public code! Abner Chang of HPE has submitted multiple patches with RISC-V support for various components of EDK-II.

[PATCH 0/3] *** EDK2 base tools support RISC-V processor***

EDK2 base tools support RISC-V arch. EDK2 build tool changes to generate RISC-V PE/Coff image from RISC-V ELF file, handle RISC-V relocations and generate EDK2 FW with RISC-V image machine type.

BaseTools: Support build RISC-V PE/Coff image.
The changes on BaseTools is for building RISC-V ELF image and PE/Coff Image. Also to generate FW and FV for RISC-V arch.     

[PATCH 0/2] *** EDK2 MDE for RISC-V processor ***

MdePkg: MDE implementations for RISC-V arch. The implementations of RISC-V MDE base libraries.

    Add RISC-V architecture image file machine code.
    Add RISC-V architecture relocation type.    
    Add RISC-V architecture context buffer.
    Add RISC-V architecture exception types.
    Add RISC-V architecture PXE tag definition.    
    Add RISC-V architecture EFI image machine type.
    Add RISC-V architecture removable media boot path.
    Add RISC-V architecture processor binding.
[PATCH] OvmfPkg/PciHostBridgeDxe: [RISC-V] Add back OVMF PciHostBridge module.

Use OVMF PCI host bridge driver as the RISC-V platform BUS.
This driver is used by RISC-V Virtualization package (RiscVVirtPkg).
Currently the platfrom spec for RISC-V is not yet ready, thus we use PCI host bridge in temporarily.

[PATCH] RiscVVirtPkg: RISC-V QEMU package.

This is RISC-V QEMU package. The image which built from this package can be launched on QEMU RISC-V port (not official QEMU). RiscVVirtPkg utilizes below modules from EDK2 OVMF package,
 – PciHostBridge DXE driver.
   Use PCI host bridge driver as RISC-V platform bus spec for adopting PC/AT components.
 – QemuFwCfgLib
   QEMU firmware configuration.
 – OVMF ACPI timer lib.
 – QemuFlashFvbServicesRuntimeDxe
 – QemuVideoDxe
 – XenIoPciDxe

[PATCH] RiscVPkg: RISC-V processor package.

 New processor package added to EDK2 open source for RISC-V.
[PATCH] MdeModulePkg/DxeIplPeim: RISC-V arch DxeIpl.

The implementation of RISC-V DxeIpl.

This is only the first round of these multiple patches, given initial discussion it is likely there will be another round. In the discussion for this patch, it appears there is more support upcoming, not yet public. In the thread, Abner mentioned:

“The UEFI/PI ECR for RISC-V is ready but not yet send to UEFI for review. I have been told to upstream RISC-V code first and then submit the spec. I will confirm this again.”

I am looking forward to seeing what happens with the RISC-V UEFI port, and seeing some consumer devices based on RISC-V!

For more info, see the various threads on the EDK2-devel list:

lowRISC project enters GSoC 2016

“The lowRISC is taking part in the 2016 Google Summer of Code (GSoC). Additional projects mentored by other organisations that may benefit lowRISC and the open source hardware eocsystem include multi-threaded TCG in QEMU, developing a RISC-V processor model for ArchC, improving the RISC-V port of Coreboot, or working on cross-bootstrap in Debian. Also see the MyHDL projects. Student applications are open between March 14th and March 25th. Project ideas (in no particular order):

Porting musl libc to RISC-V
Improve device-tree support for the Linux RISC-V port
Schematic Viewer for Netlists (SVG/JavaScript)
An alternative flow for ice40 place and route
Port a teaching operating system to the lowRISC platform
Integrate more open-source IP for lowRISC on FPGAs
Implement a Trusted Execution Environment
Trace-debug analysis tool
Generic hardware/software interface for software-defined radio
Implement a SPIR-V front end for Nyuzi
Port an operating system kernel to Nyuzi”

RISC-V/LowRISC update

The recent RISC-V workshop is over, presentations are online, videos are not yet online:

RISC-V and coreboot:

Click to access Tues1345%20riscvcoreboot.pdf


Click to access Tues1415%20RISC-V%20and%20UEFI.pdf

There is some post-workshop coverage here:

LowRISC, a related project to RISC-V is also making progress. From the below EE Times article:

“The LowRISC project at the University of Cambridge is attracting interest as the likely first source of real development hardware. The team which includes members of the Raspberry Pi project hopes to have first silicon this year and plans to make development boards available in 2017, likely for $50-100.”

I missed this news, it is interesting to see Google, HP, and Oracle getting involved with RISC-V.


Firmware and RISC-V workshop

At the 3rd RISC-V Workshop, there have been presentations by coreboot and UEFI. The below blog has some notes on these presentations:

Apparently, someone is porting UEFI to RISC-V. I wonder what company is funding/doing it??

updated RISC-V specs

Click to access riscv-compressed-spec-v1.9.pdf

A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović,

“The RISC-V Compressed Instruction Set Manual, Version 1.9,”

EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-209, 5 Nov 2015.


coreboot changes

The coreboot blog has a long post, which covers the last five weeks of changes, and there were a lot: 314 commits. Some highlights:

Over one third of the commits covers Intel Skylake development, where boards and chipset code saw misc improvements and tons of clean ups.

There also was a notable effort of unifying common code across the more recent Intel SoCs, removing lots of duplicated code all over the place.

On x86, the romstage is now relocated for its final location in CBFS by cbfstool, obsoleting the old approach that had us link it twice, once to determine its final size and then to the actual location it’s supposed to run from. In the future this same approach may be extended to other files that need to be executed in place such as the FSP binary.

The romstage change eliminated the need for cbfstool’s “locate” command, and so it was removed. cbfstool also saw other extensions, the biggest one a compatible change to the format to allow for per-file attributes in CBFS. These attributes can contain additional information about a file, currently the compression method and uncompressed size of a file. cbfstool and the build system were extended to allow compressing files, libpayload is able to uncompress these files.

On the AMD side, there were various bugfixes both for new (merlin falcon) and old (Fam10) chipsets.

ARM64 and Tegra210 saw various bugfixes and improvements to power use. For the latter, coreboot also learned how to reserve memory for other functions than the main processor.
Rockchip’s RK3288 ARMv7 SoC also saw a number of bug fixes and the code was restructured to use a single mainboard directory for a large number of very similar Google Veyron mainboards based on that SoC.

Our RISCV support now boots on the Spike simulator which (besides supporting a wider variety of emulators) is notable because unlike the QEmu RISCV support, Spike supports RISCV’s revised ABI.
Speaking of emulators, recent versions of qemu-x86 expect the firmware to initialize the LAPIC, which we now do.

The ongoing effort to move CPU microcode into CBFS (and to store these as binaries in 3rdparty/blobs instead of header files in the main sources) saw some progress.

Lots of interesting things were omitted above. Full post:

MIAOW and Raven3 at HotChips

HotChips ended this week. As mentioned in the last post on this event:

not only is the Open Source ISA RISC-V there, but so was an Open Hardware GPU, MIAOW (Many-core Integrated Accelerator of Wisconsin):

Rick Merritt of EE Times has written a new articles on both the RISC-V ISA and MIAOW GPU:

RISC-V Raven processor talk at HotChips

HotChips 2015 is happening in Cupertino, California later this month, 23-25th. Today Krste Asanovic posted a message on the RISC-V blog:

RISC-V at HotChips: Analyst Kevin Krewell has posted a HotChips preview at EE Times, which mentions the RISC-V Raven-3 presentation to be made in the last session at HotChips by Yunsup Lee.  UC Berkeley will again be sponsoring a table at HotChips to promote RISC-V, so please drop by if you’ll be there and want to chat about RISC-V uptake.

Hot Chips is a symposium on High Performance Chips, sponsored by the IEEE Technical Committee on Microprocessors and Microcomputers, in cooperation with ACM SIGARCH. The RISC-V presentation is on the “Raven” processor:

Raven: A 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking
by: Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian Richards, Elad Alon, Borivoje Nikolic and Krste Asanovic, University of Berkeley

The EE Times blog article, by Kevin Krewell of Tirias Research, gives a good overview of all the vendors presenting at HotChips, focusing on the traditional ones (Intel, ARM, AMD, etc.), and calls RISC-V an “odd duck”. 🙂

The last session on Tuesday is traditionally the main “big” processor session. […] The odd duck in the session is an implementation of UC Berkeley RISC-V Vector Processor. Last year the Berkeley contingent showed off RISC-V instruction set in the break area, but now with a real chip, they made it to inside the auditorium. It’s not too often you see a chip design of this integration and complexity coming from academia. What started as a project to give universities a royalty-free and extendable CPU architecture to build on, has gained traction, especially in India and Asia for development purposes.”

RISC-V and Open Hardware aside, there are many other interesting presentations at Hot Chips 2015, including talks from Intel, ARM, AMD, and others. There are a handful of other Open Hardware/Maker-related talks, eg: Adapteva is talking about their Kickstarted chip, and Univerisity of Wisconson’s MIAOW project, an OpenGL API-compatible GPGPU.

ORConf 2015 announced

What: ORConf 2015
When: October 9-11, 2015
Where: Geneva, Switzerland
Who: Open Hardware OEMs/IHVs/ODMs/IBVs/ISVs
Why: NDAs, IP licensing fees, firmware blobs, non-ownership

Here’s the announcement from the lowRISC announcement mailing list:

Please join us October 9th-11th in Geneva, Switzerland for ORConf 2015 [1]. The event is kindly being hosted by CERN at the IdeaSquare. Last year’s ORConf was home to the first public talk on lowRISC and we’re pleased this year it will also be hosting a series of lowRISC and RISC-V discussions, serving as a European lowRISC and RISC-V workshop. ORConf has in recent years grown to cover a range of open source hardware topics beyond the original OpenRISC focus. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few. The event will run from 13:00 until 18:30 on Friday, 09:30 until 19:30 on Saturday, and from 09:30 until 15:30 on Sunday. Friday will consist primarily of breakout sessions, planning, and discussion regarding lowRISC. If you are already contributing or your are thinking of getting involved and want to learn more, you are very welcome to join us. If you would like to present, please do submit a proposal either via the link at the ORConf website or to me at We hope to see many of you there – please register here: [2]. If you haven’t been to the blog for a while and are wondering what’s been going on in the world of RISC-V and lowRISC, you may be interested in our summary of the presentations at the second RISC-V workshop [3].


LowRISC is related to RISC-V, both are Open Source Hardware ISAs, which IMO is needed for Open Source Hardware (and Free Hardware), else we’ll always have to deal with NDAs, IP licensing fees, and — on most platforms — closed-source firmware blobs, and not knowing what the system is actually doing behind the scenes. I hope the Linux Foundation, FreeBSD Foundation, Open Source Hardware Foundation, the Free Software Foundation (for Free Hardware) and other related groups plan on using CrowdSupply — or other crowdfunding source — to fund lowRISC/RISC-V-based hardware. You can’t expect change from the top, Microsoft and Apple drive the ISAs and have zero incentive to reduce NDAs, IP licensing fees and firmware blobs. I hope that in a few years Purism starts using RISC-V (or lowRISC, or OpenRISC) for their systems!

OpenRISC is a “Free Hardware” ISA, a GPL-based instruction set that has been around for a while. This conference is apparently open to other topics beyond OpenRISC, such as the newer BSD-licensed lowRISC and RISV-V peers. I don’t know why, but I’m guessing that OpenRISC hasn’t gotten more traction is due to hardware’s community’s fear of GPL, or they were just too early to market. It might be nice for the FSF to help OpenRISC more than they have, since it is the only GPL ISA, pehaps the heart of their Free Hardware? Then again, BSD-based RISC-V/lowRISC can easily be GPL’ed.

Note that the Call for Papers is open, there’s time to submit a talk…

RISC-V Privileged Architecture Draft seeks feedback

RISC-V is an up-and-coming alternative Open Hardware architecture, BSD-licensed, with no IP. It isn’t ready for use today, may grow into a viable alternative in the coming months. Currently, they are looking for feedback for their Privileged Architecture Draft Specification:

“This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the website. We hope to freeze the core parts of this privileged architecture specification later this year. We will very shortly be releasing an updated Spike simulator and Linux port conforming to the proposed standard, along with QEMU updates to follow. A draft version of v1.8 of the spec is expected this summer, with a frozen v2.0 targeted for the fall. The draft Supervisor Binary Interface will be released with the next privileged ISA draft. It includes common functionality for TLB shootdowns, reboot/shutdown, sending inter-processor interrupts etc etc. This is a similar idea to the PALCode on the Alpha.”

They’re quite eager for some security feedback, in case there’re any hardware security experts here willing to help them out:

More Information:

Click to access riscv-privileged-spec-v1.7.pdf

Click to access riscv-privileged-workshop-june2015.pdf