RISC-V is an up-and-coming alternative Open Hardware architecture, BSD-licensed, with no IP. It isn’t ready for use today, may grow into a viable alternative in the coming months. Currently, they are looking for feedback for their Privileged Architecture Draft Specification:
“This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the http://www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year. We will very shortly be releasing an updated Spike simulator and Linux port conforming to the proposed standard, along with QEMU updates to follow. A draft version of v1.8 of the spec is expected this summer, with a frozen v2.0 targeted for the fall. The draft Supervisor Binary Interface will be released with the next privileged ISA draft. It includes common functionality for TLB shootdowns, reboot/shutdown, sending inter-processor interrupts etc etc. This is a similar idea to the PALCode on the Alpha.”
They’re quite eager for some security feedback, in case there’re any hardware security experts here willing to help them out:
More Information:
Click to access riscv-privileged-spec-v1.7.pdf
Click to access riscv-privileged-workshop-june2015.pdf
https://blog.riscv.org/2015/05/risc-v-draft-privileged-architecture-version-1-7-released/
http://riscv.org/
http://www.lowrisc.org/
Firmware Security 