Tag: RISCV

Tianocore to get RISC-V port

~ hucktech ~ 2 Comments

UEFI’s Tianocore implementation has built-in support for Intel/AMD and ARM. The RISCV-V port has been in a branch. Now it appears RISC-V is about to become part of the main branch, with 2 new packages, RiscVPkg and RiscVVirtPkg:

RISC-V is a new ISA which was designed to support computer architecture research and education. But now it becomes a standard open architecture for industry implementations. RISC-V edk2 project is to create a new processor binding in UEFI spec and to have RISC-V edk2 implementation. The goal is to have RISC-V edk2 port as the firmware reference for RISC-V platforms. Also, this proves the UEFI spec and edk2 implementation are flexible and well deisgned for adopting any processor architecture. The following modules are related to edk2 RISC-V port:

RiscVPkg – RISC-V processor package. This package provides RISC-V processor related protocols/libraries accroding to UEFI specification and edk2 implementations.

RiscVVirtPkg – RISC-V QEMU port. This is the RISC-V platform which is based on QEMU implementation. We use PC/At bus architecture as RISC-V platform bus spec. The image built from this package can be launched by QEMU RISC-V port.

https://bugzilla.tianocore.org/show_bug.cgi?id=2532

https://bugzilla.tianocore.org/show_bug.cgi?id=2533

https://github.com/riscv/riscv-uefi-edk2-docs

https://github.com/tianocore/edk2-staging/tree/RISC-V

RISC-V Privileged Architecture Draft seeks feedback

~ hucktech ~ Leave a comment

RISC-V is an up-and-coming alternative Open Hardware architecture, BSD-licensed, with no IP. It isn’t ready for use today, may grow into a viable alternative in the coming months. Currently, they are looking for feedback for their Privileged Architecture Draft Specification:

“This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the http://www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year. We will very shortly be releasing an updated Spike simulator and Linux port conforming to the proposed standard, along with QEMU updates to follow. A draft version of v1.8 of the spec is expected this summer, with a frozen v2.0 targeted for the fall. The draft Supervisor Binary Interface will be released with the next privileged ISA draft. It includes common functionality for TLB shootdowns, reboot/shutdown, sending inter-processor interrupts etc etc. This is a similar idea to the PALCode on the Alpha.”

They’re quite eager for some security feedback, in case there’re any hardware security experts here willing to help them out:

More Information:

Click to access riscv-privileged-spec-v1.7.pdf

Click to access riscv-privileged-workshop-june2015.pdf

https://blog.riscv.org/2015/05/risc-v-draft-privileged-architecture-version-1-7-released/
http://riscv.org/
http://www.lowrisc.org/