RISC-V implementations filled with blobs

Intel, ARM, and especially POWER will be loving this moment:

All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied “openness” but as we can see that is not so. There’s blobs in HiFive.



2 thoughts on “RISC-V implementations filled with blobs

  1. Pingback: coreboot for HiFive Unleashed | Firmware Security

  2. Pingback: SiFive: DDR controller configuration register values unleashed! | Firmware Security

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