Ivan Hu of Canonical announced the release of FWTS 17.03.00. There’s a new SBBR test, and a slew of bugfixes.
New Features :
* ACPICA: Update to version 20170224
* sbbr: Add “–sbbr” flag to support running SBBR Tests.
* acpi: iort: Add support for SMMUv3
Linaro does regular drops of core tools, and these days they’re using GCC v6.x, and GCC has a few new language features and target architecture features recently. Excerpting the Linaro announcement:
The Linaro GCC 6.3-2017.02 Release is now available. […] The Linaro binary toolchain is a collection of x86-hosted GNU cross-toolchains targeting a variety of ARM architecture targets. Linaro TCWG provides these toolchains as a service to our members. Due to hardware availability, system-image availability, validation complexity, and user-base size, not all host and target toolchain combinations can be validated by Linaro with the same rigor. The most rigorously validated targets are little-endian and hardfloat implementations of the 32-bit ARMv7 (arm), 32-bit ARMv8 (armv8), and 64-bit ARMv8 (aarch64) architectures. Linaro recommends those targets to our members. […] The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc’s memcpy API. Linaro recommends using the 64-bit x86_64 host toolchains as the 32-bit i686 host toolchains and the 32-bit mingw host toolchains will only be provided as long as there is sufficient member interest to justify their continued availability. […] The GCC 6 Release series has significant changes from the GCC 5 release series. For an explanation of the changes please see the following website. For help in porting to GCC 6 please see the following explanation. […]
See the full announcement for more details:
We are proud to announce that our TERES I laptop is complete. We have assembled units and now working on the software. The building instructions are uploaded here and you can see that it’s pretty easy to build one yourself. This weekend in Bruxell at FOSDEM we will have table in Hall AW where every one could touch and play with the very first built laptops. All spare parts are uploaded at the web. Hardware CAD files and Linux build scripts are on GitHub. TERES I is completely designed with KiCAD FOSS so everyone can download and learn, study, edit, modify. Hardwarewise everything is OK and works, the software need some care to be completed, power supply management, Linux distribution, and few more details need attention, but we hope everything to be complete till Friday!
TERES I was the first king of the Odrysian state of Thrace where Plovdiv is also located.
One of the files on github mentions:
* Clean binary blobs if possible
There’s an article by ARM in EE Times on vehicle security. This provides a non-TPM-centric perspective, which many of these articles focus on.
Quoting the press release:
Automotive safety hypervisor announced for ARM Cortex-R52
OpenSynergy paves way for next-generation autonomous devices with virtualization for ARM’s most advanced real-time processor
Berlin, Germany and Cambridge, UK, January 18, 2017. OpenSynergy is developing the industry’s first software hypervisor for the ARM® Cortex®-R52 processor, ARM’s most advanced real-time safety processor. The hypervisor turns any chip based on the Cortex-R52 into several virtual machines capable of simultaneously executing separate software tasks. To address increasing software complexity in devices such as autonomous vehicles and industrial control systems, this approach allows for the isolation of safety-critical functions from those that require less stringent control. In addition, it enables the consolidation of applications onto fewer electronic control units (ECUs) to both manage complexity and reduce cost. “Mass-market autonomous vehicles will be engineered with greatly enhanced ECU compute capabilities and the ability to safely manage far more complex software stacks,” said Richard York, vice president of embedded marketing, ARM. “The Cortex-R52 was purpose-built for this task, with hypervisor-enabled software separation protecting critical safety features while ensuring fast task execution. This will enable highly performant vehicles that can be fully trusted to take over from the driver.” “The ARM Cortex-R52 processor will bring virtualization technology to a much wider set of devices in the automotive market,” said Stefaan Sonck Thiebaut, CEO, OpenSynergy. “In doing so, we look forward to enabling the next generation of vehicle architecture.” The Cortex-R52 introduces hardware support for virtualization to the Cortex-R family of processors while maintaining all the functionality required for hard real-time systems. The ability to maintain deterministic execution within a hypervisor provides an ideal solution to the challenge of concurrent real-time systems in a wide array of robotic applications. OpenSynergy’s software architecture targets microcontrollers such as domain controllers. The hypervisor technology enables several real-time operating systems and AUTOSAR systems at different ASIL levels to run in parallel on the Cortex-R52.
Leif has a new blog post on using UEFI with USB pass-through.
[…]”One thing that is unsurprising, but very cool and useful, is that this works well cross-architecture. So you can test that your drivers are truly portable by building (and testing) them for AARCH64, EBC and X64 without having to move around between physical machines. ”
Checkout his previous blog post, on UEFI driver development, as well as older posts on Linaro/ARM/UEFI history.