How Does an Intel Processor Boot?

When we switch on a computer, it goes through a series of steps before it is able to load the operating system. In this post we will see how a typical x86 processor boots. This is a very complex and involved process. We will only present a basic overall structure. Also what path is actually taken by the processor to reach a state where it can load an OS, is dependent on boot firmware. We will follow example of coreboot, an open source boot firmware.[…]

6 new security advisories from Intel

Intel® Server Boards Firmware Advisory

Intel® RAID Web Server 3 Service Advisory

Intel® NUC Bios Updater Advisory

Intel® NVMe and Intel® RSTe Driver Pack Advisory

Intel® Server Board Firmware Advisory


Positive Technologies researcher finds vulnerability enabling disclosure of Intel ME encryption keys

Re: and

Intel releases 17 security advisories!

Intel® Distribution for Python 2018 for Windows Advisory

Intel® Centrino® Wireless-N and Intel® Centrino® Advanced-N products Bluetooth Driver Advisory

Intel® NUC Firmware Security Advisory

Intel® IoT Developers Kit Permissions Advisory

OpenVINO™ Toolkit for Windows Permissions Issue Advisory

Intel® Data Migration Software Improper Permissions Advisory

Intel® Driver & Support Assistant and Intel® Software Asset Manager Advisory

Intel® Extreme Tuning Utility Advisory

Intel® Baseboard Management Controller (BMC) firmware Advisory

Intel® Server Board TPM Advisory

Intel® Data Center Manager SDK Advisory

Intel® Platform Trust Technology (PTT) Update Advisory

Intel® Active Management Technology 9.x/10.x/11.x/12.x Security Review Cumulative Update Advisory

Power Management Controller (PMC) Security Advisory

Intel® CSME Assets Advisory

INTEL-SA-00086 Detection Tool DLL Injection Issue Advisory

Intel: The TPM2 Software Stack: Introducing a Major Open Source Release

A newly completed Trusted Platform Module 2.0 (TPM2) software stack is being introduced, developed to comply with the most recent Trusted Computing Group (TCG) v1.38 specification and work on any TPM2 implementation. Partnering with key players within the domain of Trusted Computing such as Infineon and Fraunhofer SIT, Intel has made large investments in code improvements and new functionality compared to the previous version. This includes the initialization of the TSS Stack development and the SAPI, TCTI and abrmd layer. Based on this development, Infineon and Fraunhofer SIT enabled the support of the Enhanced System API (ESAPI) layer, which is intended to reduce programming complexity and to simplify the use and integration of the TPM.[…]


Intel ME JTAG PoC for INTEL-SA-00086

Vulnerability INTEL-SA-00086 allows to activate JTAG for Intel Management Engine core. We developed our JTAG PoC for the Gigabyte Brix GP-BPCE-3350C platform. Although we recommend that would-be researchers use the same platform, other manufacturers’ platforms with the Intel Apollo Lake chipset should support the PoC as well (for TXE version[…]


a bit more on Intel-SA-00161 (and microcode license update)


Intel updated their document today, and revised their microcode license:

Intel-microcode has license that prevents redistribution

In case technical issues weren’t enough, the lawyers at Intel have apparently made it more difficult for some open source operating systems to use the latest Intel microcode.

PS: AMD is apparently still blocked at technical issues:

MicroPython for UEFI and Intel MicroPython-based UEFI test framework released


MicroPython for UEFI systems is available, see Brian’s edk2-devel list posting and the Tianocore wiki for more details:

Intel updates 2 security whitepapers

SMM disabling and verification techniques

3mdeb points out that there is a patent by Intel with information focused on disabling Intel SMM.

Don’t click on this link if you’re an engineer and are not allowed to view patent information.

IA32-doc: Intel Manual definitions in C and YAML

IA32-doc:: put as many definitions from the Intel Manual into machine-processable format (in this case: yaml) as possible.


  • ? OriginalNames – preserve case-sensitivity (BIOS, x2APIC, ToPA, …)
  • ? Add final Reserved field to bitfields
  • ? Possibility to split into multiple .h
  • ?? Add doxygen main page
  • ??? Add AMD
  • Find what else is missing
  • Fix 32/64 bitfields for MSR registers
  • Add possibility for bitfields to have both UINT32/UINT64 members