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lowRISC project enters GSoC 2016

“The lowRISC is taking part in the 2016 Google Summer of Code (GSoC). Additional projects mentored by other organisations that may benefit lowRISC and the open source hardware eocsystem include multi-threaded TCG in QEMU, developing a RISC-V processor model for ArchC, improving the RISC-V port of Coreboot, or working on cross-bootstrap in Debian. Also see the MyHDL projects. Student applications are open between March 14th and March 25th. Project ideas (in no particular order):

Porting musl libc to RISC-V
Improve device-tree support for the Linux RISC-V port
Schematic Viewer for Netlists (SVG/JavaScript)
An alternative flow for ice40 place and route
Port a teaching operating system to the lowRISC platform
Integrate more open-source IP for lowRISC on FPGAs
Implement a Trusted Execution Environment
Trace-debug analysis tool
Generic hardware/software interface for software-defined radio
Implement a SPIR-V front end for Nyuzi
Port an operating system kernel to Nyuzi”

http://www.lowrisc.org/docs/gsoc-2016-ideas/

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bunnie seeking feedback on lowRISC usage

Quoting bunnie’s forum post:
It’s not quite got the specs to make a decent laptop — it’s missing graphics and SATA. The effective performance of a system built around this would feel much more sluggish than a Novena, which means it’ll be tough to use on a daily basis for productivity work. It does have tagged memory and minion cores, which means it’ll be great for security and some types of I/O; but there is no integrated Ethernet controller, so application in network stacks is limited. It is also going to be the first open-to-the-RTL processor you can buy, so maybe despite the limitations some people would prefer to use it as a primary computing solution, but wondering if there aren’t other niches this can occupy.

http://www.kosagi.com/forums/viewtopic.php?pid=2556
https://twitter.com/hashtag/lowRiscWish?src=hash

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RISC-V/LowRISC update

The recent RISC-V workshop is over, presentations are online, videos are not yet online:

http://riscv.org/workshop-jan2016.html
http://riscv.org/

RISC-V and coreboot:
http://riscv.org/workshop-jan2016/Tues1345%20riscvcoreboot.pdf

RISC-V and UEFI:
http://riscv.org/workshop-jan2016/Tues1415%20RISC-V%20and%20UEFI.pdf

There is some post-workshop coverage here:
https://blog.riscv.org/2016/01/3rd-risc-v-workshop-presentations-breakouts/
http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-day-one/
http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-day-two/
http://www.adapteva.com/andreas-blog/why-i-will-be-using-the-risc-v-in-my-next-chip/
http://www.eetimes.com/document.asp?doc_id=1328620&

LowRISC, a related project to RISC-V is also making progress. From the below EE Times article:

“The LowRISC project at the University of Cambridge is attracting interest as the likely first source of real development hardware. The team which includes members of the Raspberry Pi project hopes to have first silicon this year and plans to make development boards available in 2017, likely for $50-100.”

http://www.lowrisc.org/

http://www.eetimes.com/document.asp?doc_id=1328620&

I missed this news, it is interesting to see Google, HP, and Oracle getting involved with RISC-V.

http://www.eetimes.com/document.asp?doc_id=1328561&

 

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Firmware and RISC-V workshop

At the 3rd RISC-V Workshop, there have been presentations by coreboot and UEFI. The below blog has some notes on these presentations:

http://riscv.org/workshop-jan2016.html
http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-day-one/

Apparently, someone is porting UEFI to RISC-V. I wonder what company is funding/doing it??

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lowRISC untethered release

Today the lowRISC team announced the “Untethered lowRISC release”:

Over the past several months, we’ve been working to provide a standalone or ‘untethered’ SoC. Cores in the original Rocket chip rely on communicating with a companion processor via the host-target interface (HTIF) to access peripherals and I/O. This release removes this requirement, adding an I/O bus and instantiating FPGA peripherals. The accompanying tutorial, written by Wei Song, describes how to build this code release and explains the underlying structural changes. We support both the Xilinx KC705 and the lower-priced Nexys4 DDR development boards. We would gladly welcome assistance in supporting other boards. […]

Full announcement:

http://www.lowrisc.org/blog/2015/12/untethered-lowrisc-release/
http://www.lowrisc.org/docs/untether-v0.2/
http://www.lowrisc.org/docs/untether-v0.2/release/
https://github.com/lowRISC/lowrisc-chip/
http://lowrisc.org/

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ORConf 2015 announced

What: ORConf 2015
When: October 9-11, 2015
Where: Geneva, Switzerland
Who: Open Hardware OEMs/IHVs/ODMs/IBVs/ISVs
Why: NDAs, IP licensing fees, firmware blobs, non-ownership

Here’s the announcement from the lowRISC announcement mailing list:

Please join us October 9th-11th in Geneva, Switzerland for ORConf 2015 [1]. The event is kindly being hosted by CERN at the IdeaSquare. Last year’s ORConf was home to the first public talk on lowRISC and we’re pleased this year it will also be hosting a series of lowRISC and RISC-V discussions, serving as a European lowRISC and RISC-V workshop. ORConf has in recent years grown to cover a range of open source hardware topics beyond the original OpenRISC focus. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few. The event will run from 13:00 until 18:30 on Friday, 09:30 until 19:30 on Saturday, and from 09:30 until 15:30 on Sunday. Friday will consist primarily of breakout sessions, planning, and discussion regarding lowRISC. If you are already contributing or your are thinking of getting involved and want to learn more, you are very welcome to join us. If you would like to present, please do submit a proposal either via the link at the ORConf website or to me at asb@lowrisc.org. We hope to see many of you there – please register here: [2]. If you haven’t been to the blog for a while and are wondering what’s been going on in the world of RISC-V and lowRISC, you may be interested in our summary of the presentations at the second RISC-V workshop [3].

[1] http://openrisc.io/orconf/
[2] http://goo.gl/forms/KRZux8vnyO
[3] http://www.lowrisc.org/blog/2015/06/second-risc-v-workshop-day-one/
http://www.lowrisc.org/blog/2015/06/second-risc-v-workshop-day-two/

http://www.lowrisc.org/blog/2015/08/lowrisc-at-orconf-2015/

LowRISC is related to RISC-V, both are Open Source Hardware ISAs, which IMO is needed for Open Source Hardware (and Free Hardware), else we’ll always have to deal with NDAs, IP licensing fees, and — on most platforms — closed-source firmware blobs, and not knowing what the system is actually doing behind the scenes. I hope the Linux Foundation, FreeBSD Foundation, Open Source Hardware Foundation, the Free Software Foundation (for Free Hardware) and other related groups plan on using CrowdSupply — or other crowdfunding source — to fund lowRISC/RISC-V-based hardware. You can’t expect change from the top, Microsoft and Apple drive the ISAs and have zero incentive to reduce NDAs, IP licensing fees and firmware blobs. I hope that in a few years Purism starts using RISC-V (or lowRISC, or OpenRISC) for their systems!
http://lowrisc.org/
http://riscv.org/

OpenRISC is a “Free Hardware” ISA, a GPL-based instruction set that has been around for a while. This conference is apparently open to other topics beyond OpenRISC, such as the newer BSD-licensed lowRISC and RISV-V peers. I don’t know why, but I’m guessing that OpenRISC hasn’t gotten more traction is due to hardware’s community’s fear of GPL, or they were just too early to market. It might be nice for the FSF to help OpenRISC more than they have, since it is the only GPL ISA, pehaps the heart of their Free Hardware? Then again, BSD-based RISC-V/lowRISC can easily be GPL’ed.
http://openrisc.io/

Note that the Call for Papers is open, there’s time to submit a talk…

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RISC-V Privileged Architecture Draft seeks feedback

RISC-V is an up-and-coming alternative Open Hardware architecture, BSD-licensed, with no IP. It isn’t ready for use today, may grow into a viable alternative in the coming months. Currently, they are looking for feedback for their Privileged Architecture Draft Specification:

“This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the http://www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year. We will very shortly be releasing an updated Spike simulator and Linux port conforming to the proposed standard, along with QEMU updates to follow. A draft version of v1.8 of the spec is expected this summer, with a frozen v2.0 targeted for the fall. The draft Supervisor Binary Interface will be released with the next privileged ISA draft. It includes common functionality for TLB shootdowns, reboot/shutdown, sending inter-processor interrupts etc etc. This is a similar idea to the PALCode on the Alpha.”

They’re quite eager for some security feedback, in case there’re any hardware security experts here willing to help them out:

More Information:
http://riscv.org/spec/riscv-privileged-spec-v1.7.pdf
http://riscv.org/workshop-jun2015/riscv-privileged-workshop-june2015.pdf
https://blog.riscv.org/2015/05/risc-v-draft-privileged-architecture-version-1-7-released/
http://riscv.org/
http://www.lowrisc.org/

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