The recent RISC-V workshop is over, presentations are online, videos are not yet online:
http://riscv.org/workshop-jan2016.html
http://riscv.org/
RISC-V and coreboot:
RISC-V and UEFI:
There is some post-workshop coverage here:
https://blog.riscv.org/2016/01/3rd-risc-v-workshop-presentations-breakouts/
http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-day-one/
http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-day-two/
http://www.adapteva.com/andreas-blog/why-i-will-be-using-the-risc-v-in-my-next-chip/
http://www.eetimes.com/document.asp?doc_id=1328620&
LowRISC, a related project to RISC-V is also making progress. From the below EE Times article:
“The LowRISC project at the University of Cambridge is attracting interest as the likely first source of real development hardware. The team which includes members of the Raspberry Pi project hopes to have first silicon this year and plans to make development boards available in 2017, likely for $50-100.”
http://www.eetimes.com/document.asp?doc_id=1328620&
I missed this news, it is interesting to see Google, HP, and Oracle getting involved with RISC-V.
http://www.eetimes.com/document.asp?doc_id=1328561&
