There’ve been a few presentations on porting UEFI to the RISC-V, but now there is public code! Abner Chang of HPE has submitted multiple patches with RISC-V support for various components of EDK-II.
[PATCH 0/3] *** EDK2 base tools support RISC-V processor***
EDK2 base tools support RISC-V arch. EDK2 build tool changes to generate RISC-V PE/Coff image from RISC-V ELF file, handle RISC-V relocations and generate EDK2 FW with RISC-V image machine type.
BaseTools: Support build RISC-V PE/Coff image.
The changes on BaseTools is for building RISC-V ELF image and PE/Coff Image. Also to generate FW and FV for RISC-V arch.
[PATCH 0/2] *** EDK2 MDE for RISC-V processor ***
MdePkg: MDE implementations for RISC-V arch. The implementations of RISC-V MDE base libraries.
Add RISC-V architecture image file machine code.
Add RISC-V architecture relocation type.
Add RISC-V architecture context buffer.
Add RISC-V architecture exception types.
Add RISC-V architecture PXE tag definition.
Add RISC-V architecture EFI image machine type.
Add RISC-V architecture removable media boot path.
Add RISC-V architecture processor binding.
[PATCH] OvmfPkg/PciHostBridgeDxe: [RISC-V] Add back OVMF PciHostBridge module.
Use OVMF PCI host bridge driver as the RISC-V platform BUS.
This driver is used by RISC-V Virtualization package (RiscVVirtPkg).
Currently the platfrom spec for RISC-V is not yet ready, thus we use PCI host bridge in temporarily.
[PATCH] RiscVVirtPkg: RISC-V QEMU package.
This is RISC-V QEMU package. The image which built from this package can be launched on QEMU RISC-V port (not official QEMU). RiscVVirtPkg utilizes below modules from EDK2 OVMF package,
– PciHostBridge DXE driver.
Use PCI host bridge driver as RISC-V platform bus spec for adopting PC/AT components.
– QemuFwCfgLib
QEMU firmware configuration.
– OVMF ACPI timer lib.
– QemuFlashFvbServicesRuntimeDxe
– QemuVideoDxe
– XenIoPciDxe
[PATCH] RiscVPkg: RISC-V processor package.
New processor package added to EDK2 open source for RISC-V.
[PATCH] MdeModulePkg/DxeIplPeim: RISC-V arch DxeIpl.
The implementation of RISC-V DxeIpl.
This is only the first round of these multiple patches, given initial discussion it is likely there will be another round. In the discussion for this patch, it appears there is more support upcoming, not yet public. In the thread, Abner mentioned:
“The UEFI/PI ECR for RISC-V is ready but not yet send to UEFI for review. I have been told to upstream RISC-V code first and then submit the spec. I will confirm this again.”
I am looking forward to seeing what happens with the RISC-V UEFI port, and seeing some consumer devices based on RISC-V!
For more info, see the various threads on the EDK2-devel list:
https://lists.01.org/mailman/listinfo/edk2-devel
Firmware Security 
Hehehe, looks like the Google & Coreboot guys got beaten to the punch again. Yes, I’ll admit; this made me chuckle a bit. First Benjamin Herrenschmidt and Andrei Warkentin wrt POWER(PC)64-LE (though admitted, that work is unofficial), and now Abner Chang (and probably Dong Wei is involved as well) wrt RISC-V. While I’ll readily take my hat off for ppl like Patrick Georgi and Ronald Minnich & Co. and their work on the Coreboot code base, their antagonizing attitudes towards the UEFI spec slightly rubs me the wrong way, so it’s nice to see some inappropriate claims (conflating bad implementations with bad specifications, and labelling it as an attempt at hardware vendor lock-in // down) being proven wrong by guys coming from open hardware platform development circles who just take the damn spec and run with it.
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