VU739007: IEEE P1735 broken crypto

Vulnerability Note VU#739007
IEEE P1735 implementations may have weak cryptographic protections
Date: 03 Nov 2017

The P1735 IEEE standard describes methods for encrypting electronic-design intellectual property (IP), as well as the management of access rights for such IP. The methods are flawed and, in the most egregious cases, enable attack vectors that allow recovery of the entire underlying plaintext IP. Implementations of IEEE P1735 may be weak to cryptographic attacks that allow an attacker to obtain plaintext intellectual property without the key, among other impacts. The P1735 IEEE standard describes methods for encrypting electronic-design intellectual property (IP), as well as the management of access rights for such IP. The methods are flawed and, in the most egregious cases, enable attack vectors that allow recovery of the entire underlying plaintext IP. Some of these attack vectors are well-known, such as padding-oracle attacks. Others are new, and are made possible by the need to support the typical uses of the underlying IP. In particular, the need for commercial electronic design automation (EDA) tools to synthesize multiple pieces of IP into a fully specified chip design and to provide HDL syntax errors. These flaws can be exploited by leveraging the commercial EDA tool as a black-box oracle. In addition to being able to recover entire plaintext IP, one can produce standard-compliant ciphertexts of IP that have been modified to include targeted hardware Trojans.  An adversary can recover electronic design IPs encrypted using the P1735 workflow, resulting in IP theft and/or analysis of security critical features, as well as the ability to insert hardware trojans into an encrypted IP without the knowledge of the IP owner. Impacts may include loss of profit and reputation of the IP owners as well as integrated circuits (ICs) with trojans that contain backdoors, perform poorly, or even fail completely. See the researcher’s paper for full impact details.[...]

https://www.kb.cert.org/vuls/id/739007

Standardizing Bad Cryptographic Practice
A teardown of the IEEE P1735 standard for protecting electronic-design intellectual property
Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark Tehranipoor

We provide an analysis of IEEE standard P1735, which describes methods for encrypting electronic-design intellectual property (IP), as well as the management of access rights for such IP. We find a surprising number of cryptographic mistakes in the standard. In the most egregious cases, these mistakes enable attack vectors that allow us to recover the entire underlying plaintext IP. Some of these attack vectors are well-known, e.g. padding-oracle attacks. Others are new, and are made possible by the need to support the typical uses of the underlying IP; in particular, the need for commercial system-on-chip (SoC) tools to synthesize multiple pieces of IP into a fully specified chip design and to provide syntax errors. We exploit these mistakes in a variety of ways, leveraging a commercial SoC tool as a black-box oracle. In addition to being able to recover entire plaintext IP, we show how to produce standard-compliant ciphertexts of IP that have been modified to include targeted hardware Trojans. For example, IP that correctly implements the AES block cipher on all but one (arbitrary) plaintext that induces the block cipher to return the secret key. We outline a number of other attacks that the standard allows, including on the cryptographic mechanism for IP licensing. Unfortunately, we show that obvious “quick fixes” to the standard (and the tools that support it) do not stop all of our attacks. This suggests that the standard requires a significant overhaul, and that IP-authors using P1735 encryption should consider themselves at risk.

Click to access 828.pdf

http://ieeexplore.ieee.org/document/7274481/
https://standards.ieee.org/findstds/standard/1735-2014.html

Click to access ieeep1735.pdf

 

hardware security via Domain Wall Memory

Excerpt from IEEE article:

Domain Wall Memory: The Next Big Thing in Hardware Security?

University of South Florida researchers recently set out to find a way to give consumers more bandwidth. What they stumbled upon, however, may very well become a valuable hardware network security tool. An article in IEEE Journal on Emerging and Selected Topics in Circuits and Systems details how the team originally investigated new ways to design cache using domain wall memory (DWM), which is ideal for the application due to its low standby power, fast access time and good endurance. The researchers tested a physics-based model of DWM to determine how it behaves under temperature, radiation and velocity. That’s when they inadvertently discovered that DWM’s characteristics make it a potential asset for hardware security purposes.
[…]
“Our original research sought to design new cache using DWM,” said Anirudh Srikant Iyengar, lead researcher of the group. “But once we determined how difficult hacking a system like this would be, we changed directions and started looking at hardware security. The way DWM is designed makes it extremely hard to copy. Hardware security could greatly benefit from this.”[…]

Full article:

http://ieeexplore-spotlight.ieee.org/article/domain-wall-memory-could-be-the-next-hardware-security-hack/?utm_so