Patrick Georgi on UEFI memory mapping

Patrick of Coreboot has a blog post on UEFI!

UEFI memory mapping

Recently I got into UEFI (TianoCore) development. One of UEFI’s properties is that a part of it survives the OS load and remains resident to provide a limited set of firmware services to the OS.[…]



coreboot 4.3 released

Patrick Georgi of the coreboot project has announced version 4.3 of coreboot! There are too many changes for me to excerpt the release, so I’m including most of the announcement below, with some minor whitespace editing:

Since the last release, 1030 commits by 114 authors added a net total of 17500 lines to the source code. Thank you to all who contributed! Besides the usual addition of new mainboards (14) and chipsets (various), a big theme of the development since 4.2 was cleaning up the code: 20 mainboards were removed that aren’t on the market for years (and even hard to get on Ebay). For several parts of the tree, we established tighter controls, making errors out of what were warnings (and cleaning up the code to match) and provided better tests for various aspects of the tree, and in general tried to establish a more consistent structure across the code base. Besides that, we had various improvements across the tree, each important when using the hardware, but to numerous for individual shout outs. Martin compiled a list that’s best posted verbatim. Thanks Martin!

Added 14 mainboards:
– asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804 southbridge
– esd/atom15: Bay Trail SOC mainboard using Intel’s FSP
– gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB
– google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)
– google/oak: Mediatek MT8173 SoC chromebook
– google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)
– google/veyron_emile: Rockchip RK3288 SoC board
– intel/d510mo: Native init Intel Pineview with Intel I82801GX southbridge
– intel/littleplains: Intel Atom c2000 (Rangeley) SoC board
– intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel’s FSP
– lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– purism/librem13: Intel Broadwell Laptop using Intel MRC
– sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB

Removed 20 mainboards:
– arima/hdama
– digitallogic/adl855pc
– ibm/e325, e326
– intel/sklrvp
– iwill/dk8s2, dk8x
– newisys/khepri
– tyan/s2735, s2850, s2875, s2880, s2881 & s2882
– tyan/s2885, s2891, s2892, s2895, s4880 & s4882

Improvements to mainboards:
– amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS
– asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART
– intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes
– ACPI fixes across various platforms
– Many individual fixes to other mainboards
Continued updates for the Intel Skylake platform
– google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT support
– intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support

Build system:
– Update build to use FMAP based firmware layout with multiple cbfs sections
– Enable Kconfig strict mode – Kconfig warnings are no longer allowed.
– Enable ACPI warnings are errors in IASL – warnings are no longer allowed.
– Tighten checking on toolchains and give feedback to users if there are issues
– Updates to get the ADA compiler to work correctly for coreboot
– Various improvements to Makefiles and build scripts
– Cleanup of CBFS file handling

– cleanups and improvements to many of the utilities
– cbfstool: Many fixes and extensions to integrate with FMAP
– Add amdfwtool to combine AMD firmware blobs instead of using shell scripts.
– Toolchain updates: new versions of GMP & MPFR. Add ADA.
– Updates for building on NetBSD & OS X

– SeaBIOS: Update stable release to 1.9.0
– coreinfo: fix date, hide cursor, use crosscompiler to build
– libpayload: updates for cbfs, XHCI and DesignWare HCD controllers

– Added 1 soc: mediatek/mt8173
– Various fixes for ARM64 platforms

– Added 2 northbridges: intel/pineview & x4x
– Removed 1 northbridge: intel/i440lx
– Added 1 southbridge: intel/fsp_i89xx
– Removed 2 southbridge(s): intel/esb6300 & i82801cx
– Rename amd/model_10xxx to family_10h-family_15h.
– ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET entries
– Work in many areas fixing issues compiling in 64-bit
– Numerous other fixes across the tree
Areas with significant work on updates and fixes
– cpu/amd/model_fxx
– intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode
– nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes
– nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other changes
– nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup
– soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes
– soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.
– soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support
– sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes

– Imgtec Pistachio: Memory, PLL & I2C fixes, add reset

– Expand functionality for ite/it8718f & nuvoton/nct5572d superio devices
Added 3 SIOs
– intel/i8900
– winbond/w83667hg-a & wpcd376i
Removed 6 SIOs
– fintek/f71889
– ite/it8661f
– nsc/pc8374 & pc97307
– nuvoton/nct6776
– smsc/fdc37m60x

– Several updates for reading EDID tables

– Commonlib: continued updates for cbfs changes
– Work on getting license headers on all coreboot files
– Drop the third paragraph of GPL copyright header across all of coreboot

3rdparty/blobs: Update to CarrizoPI (Binary PI 1.5)

Full announcement:


coreboot update

Patrick Georgi posted an update to the coreboot blog with changes. coreboot has recently started doing more regular status updates via it’s blog. It is nice to have a regular update to coreboot, I wish UEFI and U-Boot had such a fresh news source.

A few excerpts of the changes are listed below, see full blog post for entire report:

The leading themes were the removal of support for old mainboards, and the integration of more non-AGESA AMD support code for Family 10h to 15h that spans everything from fixes to memory configuration to workarounds to problems in the SATA controller, to new feature development, enabling CC6 power-state support and everything in-between.”

Other chipset level contributions provided bug fixes to the drivers supporting Intel’s Skylake and AMD’s newer chipsets and mainboards (Kabini, Merlin Falcon, Mullins).

Also new is the Intel i8900 southbridge support that can be used with Sandy Bridge and Ivy Bridge, with an Intel reference board, the stargo2, and the SUNW Ultra40m2 board support.

Automated testing now also covers intelvbttool.

More information:

coreboot update

Last week Patrick Georgi posted a new entry to the coreboot blog.

There is support for 4 new boards: 2 Google boards, google/chell and google/lars, and 2 Asus boards, KFSN4-DRE and KGPE-D16. There were improvements to cbfstool, libpayload, superio and i2c chip drivers. The project has udpated their automated testing, and related code cleanup. There is a new lint tool for Kconfig files, see util/lint/kconfig_lint. It appears there is some fuzzing infrastructre being setup, including afl support! Some unmaintained, untested driver code was removed, and there is a maintainer-related script to help, see util/scripts/maintainers.go.

“The ongoing effort to support booting in long mode (64 bit) on AMD64 progressed by the integration of changes to make SMM handling and AMD chipset drivers 64bit clean.”

“Sandybridge now initializes CPUs serially for robustness reasons, and Intel FSP supports loading microcode from coreboot.”

“All related chipsets also saw significant improvements, of which the still ongoing effort to provide non-AGESA implementations for the Fam15h CPU, as well as a ton (metric, in case you’re curious) of bugfixes and feature developments (for example Suspend to RAM) for all AMD CPUs starting with K8 is particularly notable.”

Full blog post:

coreboot 4.2 released

Patrick Georgi posted the announcement of coreboot 4.2 to the coreboot blog today. Below is excerpt of announcement, see blog post for full details:

“Halloween 2015 release – just as scary as that sounds”

Since 4.1, 936 commits by 90 authors, increasing the code base by approximately 17000 lines of code, 35 new contributors, more than 34 active developers. […] There was some limited testing to make sure that the code is usable, and it boots on some devices. A structured test plan will only become part of the release procedure of future versions. […]  This is also the first release that will be followed by the removal of old, unused code. There will be a policy on how to announce deprecation and removal of mainboard and chipset code for future releases. Changes since 4.1:

Build system:
– Store a minimized coreboot config file in cbfs instead of the full config
– Store the payload config and revision in CBFS when that info is available
– Add -compression option for cbfs-files-y. Valid entries are now -file, -type, -align, and -compression
– Change Microcode inclusion method from building .h files to pre-built binaries
– Update Builder tests for each commit to test utilities and run lint tools
– Many other small makefile and build changes and fixes
– Remove expert mode as a Kconfig option

– Many fixes and updates to many utilities (158 total commits)
– ifdtool: Update for skylake, handle region masks correctly
– crossgcc: Update to gcc 5.2.0
– kconfig: Add strict mode to fail on kconfig errors and warnings
– vgabios: Significant fixes to remove issues in linking into coreboot code
– Add script to parse MAINTAINERS file
– Add Kconfig lint tool
– Create a common library to share coreboot routines with utilities
– Significant changes and cleanup to cbfstool (81 commits). Major changes:
– Update cbfstool to change the internal location of FSP binaries when adding them
– Decompress stage files on extraction and turn them into ELF binaries
– Header sizes are now variable, containing extended attributes
– Add compression tags to all cbfs headers so all cbfs files can be compressed
– Add and align CBFS components in one pass instead of two
– Add XIP support for X86 to relocate the romstage when it’s added
– Removed locate command as it’s no longer needed
– Add bootblock and cbfs_header file types so the master header knows about them
– Prefer FMAP data to CBFS master header if FMAP data exists
– Add hashes to cbfs file metadata for verification of images

– SeaBIOS: update stable release from 1.7.5 to 1.8.2
– Libpayload had some significant changes (61 commits). Major changes:
– Add support for fmap tables
– Add support for SuperSpeed (3.0) USB hubs
– Updates and bugfixes for DesignWare OTG controller (DWC2)
– Add video_printf to print text with specified foreground and background colors
– Updates to match changes to cbfs/cbfstool
– Add cbgfx, a library to show graphics and text on a display
– Read cbfs offset and size from sysinfo when available

– fsp_baytrail: Support Baytrail FSP Gold 4 release
– AMD binary PI: add support for fan control
– Work to get AMD AGESA to compile correctly as 64-bit code
– Add standalone (XIP) verstage support for x86 to verify romstage

– New Mainboards:
– apple/macbookair4_2 – Sandy/Ivy Bridge with Panther / Cougar point chipset
– asus/kgpe-d16 – AMD Family 10, SB700/SR5650 platform
– emulation/spike-riscv – RISCV virtualized platform
– google/chell – Intel Skylake chrome platform
– google/cyan – Intel Braswell chrome platform
– google/glados – Intel Skylake chrome platform
– google/lars – Intel Skylake chrome platform
– intel/kunimitsu – Intel Skylake chrome platform
– intel/sklrvp – Intel Skylake reference platform
– intel/strago – Intel Braswell chrome platform
– Cleanups of many mainboards – several patches each for:
– amd/bettong
– getac/p470
– google/auron, google/smaug and google/veyron_rialto
– pcengines/apu1
– siemens/mc_tcu3
– Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark and speedy) mainboards into the single google/veyron mainboard directory

– Add EM100 ‘hyper term’ spi console support in ramstage and smm
– Add console support for verstage

– armv7: use asm coded memory operations for 32/16 bit read/write
– Many cleanups to the nvidia tegra chips (40 patches)

– Add trap handling
– Add virtual Memory setup

– Remove and re-add Rangeley and Ivy Bridge / panther point FSP platforms
– Update microcode update parser to use stock AMD microcode blobs from CBFS
– ACPI: Align FACS to 64 byte boundary. Fixes FWTS error
– AMD/SB700: Init devices in early boot, restore power state after power failure. Add IDE/SATA asl code
– Add initial support for AMD Socket G34 processors
– Add tick frequency to timestamp table to calculate boot times more accurately
– Unify X86 romstage / ramstage linking to match other platforms
– Start preparing X86 bootblock for non-memory-mapped BIOS media
– cpu/amd/car: Add Suspend to RAM (S3) support
– Native VGA init fixes on several platforms
– Significant updates to FSP 1.1 code for cleanup and cbfstool changes
– SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to prevent the memory sinkhole smm hack
– Add native text mode support for the Aspeed AST2050
– w83795: Add support for for fan control and voltage monitoring
– Intel GMA ACPI consolidation and improvements
– Set up the 8254 timer before running option ROMs
– Resource allocator: Page align memory mapped PCI resources

– Derive fmap name from offset/size
– Several edid fixes
– Updates to cbfs matching changes in cbfstool


– AMD Merlin Falcon: Update to CarrizoPI (Binary PI 1.4)
– AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)
– Update microcode to binary blobs. Remove old .h microcode files

– Update the code to determine the write protect line gpio value
– Several updates to futility and image_signing scripts
– Update crossystem to accommodate Android mosys location
– Support reboot requested by secdata
– Add NV flag to default boot legacy OS

More information: