coreboot GSoC updates (RISC-V, FlashROM, SerialICE)

Wow, the coreboot blog is busy, a lot of GSoC activity to catch up to!

Jneuschaefer is doing RISC-V updates to coreboot….

[GSoC] Better RISC-V support, week #2

[GSoC] Better RISC-V support, week #3

Hatim Kanchwala is working on FlashROM…

[GSoC] Multiple status register support, week #1 and #2

Antonello Dettori is working on SerialICE:

[GSOC] Panic Room, week #2

coreboot GSoC update: RISC-V and SerialICE

The last two blog posts on the coreboot blog are by two students working on their Google Summer of Code (GSoC) project. Both sound very interesting.

Jonathan Neuschäfer is improving coreboot’s support for RISC-V platforms, which was initially added in 2014.

Antonello Dettori is working on improving SerialICE, “which is one of the main tools used in reverse engineering an OEM BIOS”, including coreboot integration.

More information: