https://itpeernetwork.intel.com/intel-processors-fpga-better-together/
Tag: Xeon
Intel Xeno Phi memory modes
James Reinders has an article in InsideHPC describes Intel XeonPhi memory modes:
[…]In this article, I will discuss one of the “mode” options that Intel Xeon Phi processors have to offer unprecedented configurability: memory modes. For programmers, this is the key option to really study because it may inspire programming changes. In my next article, I’ll tackle the other mode option (cluster modes). The memory modes allow the MCDRAM to be used as either a high bandwidth cache or a high bandwidth memory, or a little of each.[…]
http://insidehpc.com/2017/03/intel-xeon-phi-memory-mode-programming-mcdram-nutshell/
Intel to add ‘deep learning’ instructions to Xeon
Piotr Luc of Intel submitted a patch to the Linux kernel, adding ‘deep learning’ instrutions for future Xeon processors.
https://lkml.org/lkml/2016/10/12/530
[PATCH] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features.
AVX512_4VNNIW – Vector instructions for deep learning enhanced word variable precision.
AVX512_4FMAPS – Vector instructions for deep learning floating-point single precision.
The new instructions are to be used in future Intel Xeon & Xeon Phi processors.
The spec can be found in Intel Software Developer Manual or in Instruction Set Extensions Programming Reference.
See https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf.
Intel roadshow for Xeon Phi code modernization
Intel, in partnership with Bayncore, is doing a free roadshow, 1-day workshop in a few European cities, on “code modernization” for the Intel Xeon Phi processor. So far, Dublin, Cambridge. and Barcelona are the only 3 cities listed in the tour. The event is free, so if you’re in the area, use Intel System Studio, and do parallel processing and other coding techniques that need “modernization”, check out this event. Agenda:
INTEL TECHNOLOGY PLATFORM FOR HPC & PROCESSOR UPDATE
MEET INTEL PARALLEL STUDIO XE 2016 – WHAT’S NEW?
OPTIMIZE AND PERFORM WITH INTEL MPI
HPC MEETS BIG DATA – CODING HIGH-PERFORMANCE ANALYTICS IN C++ USING INTEL’S NEW DATA
ANALYTICS ACCELERATION LIBRARY
BEST PRACTICES FOR VECTORIZATION – PARALLELISM AT CORE LEVEL (SIMD)
TUTORIAL – REAL WORLD EXAMPLES FOR VECTORIZATION
CODE OPTIMIZATION IN A 3D DIFFUSION MODEL
CASE STUDY – PAIRWISE SEQUENCE ALIGNMENT WITH THE SMITH-WATERMAN ALGORITHM
http://www.inteldevconference.com/
http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html
Intel to use Xeon E3-1500M v5 in notebooks
Last week Intel announced the upcoming Xeon Processor E3-1500M v5 Product Family for notebooks. This is the 6th Generation Intel Core family based on Skylake architecture.
“Intel Xeon-based mobile workstations will have key features such as error-correcting code memory that automatically detects and repairs errors on-the-fly that cause data corruption and system crashes for peace-of-mind reliability. These new systems will also enjoy the benefits of the unique hardware-assisted security, manageability, and productivity capabilities of Intel vPro Technology. Mobile workstations featuring Intel Xeon will also feature Thunderbolt 3 – the USB-C that does it all.”
http://blogs.intel.com/technology/2015/08/bringing-intel-xeon-to-notebook-pcs/
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