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ARM big.LITTLE and cache flushing

[[
UPDATE: Here’s a message from Mark Rutland of ARM that clarifies some issues in Mono blog post:

https://lists.linaro.org/pipermail/linaro-toolchain/2016-September/005900.html

]]

Below is an excerpt of an email from Riku Voipio to the Linaro cross-distro and toolchain lists, about the recent ARM big.LITTLE issue discovered by the Mono project:

As painfully found out by mono team, if big/little cores have different cache line sizes, __clear_cache doesn’t work as expected. This affects any home-grown cache flushing mechanism as well.
Protip, if you suspect your application issues might related to big.LITTLE, use taskset(1) or hwloc-bind(1) to tie the process to either big or little cluster (or just a single core).

Here’s an excerpt from the Mono blog post (spoiler alert: it’s the final paragraph):

[…] Summary: Some ARM big.LITTLE CPUs can have cores with different cache line sizes, and pretty much no code out there is ready to deal with it as they assume all cores to be symmetrical. Worse, not even the ARM ISA is ready for this. An astute reader might realize that computing the cache line on every invocation is not enough for user space code: It can happen that a process gets scheduled on a different CPU while executing the __clear_cache function with a certain cache line size, where it might not be valid anymore. Therefore, we have to try to figure out a global minimum of the cache line sizes across all CPUs. Here is our fix for Mono: Pull Request. Other projects adopted our fix as well already: Dolphin and PPSSPP.

More info:

http://www.mono-project.com/news/2016/09/12/arm64-icache/

https://lists.linaro.org/pipermail/linaro-toolchain/2016-September/005899.html

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