will be a FOSS Verilog-to-Bitstream FGPA synthesis flow for Xilinx 7-Series FPGAs and iCE40. It is under construction.
aims at documenting the Xilinx 7-series bit-stream format, a prerequisite to building Open Source tools to generate bit-streams for those devices. The information currently on this page is a sneak preview for the kind of information Project X-Ray will provide. Currently the work focuses on the Artix-7 xc7a50tfgg484-1 device. But we hope to be able to provide documentation for all Xilinx 7-Series, UltraScale, and UltraScale+ devices in the long term. Right now we focus on the region SLICE_X12Y100:SLICE_X27Y149 on the xc7a50tfgg484-1 device (configuration frames 0x00020500:0x000208ff). The immediate goal of the project is to provide tools to create bit-streams for partial reconfiguration of this region only.