The US DoD has a new grant offered for a side-channel attack tool:
The Defense Advanced Research Projects Agency (DARPA) Small Business Programs Office (SBPO) is issuing an SBIR/STTR Opportunity (SBO) inviting submissions of innovative research concepts in the technical domain of side channel security. In particular, DARPA is interested in the feasibility of effective pre-silicon side channel and fault injection estimation. These vulnerabilities are of interest to this program only in the context of emissions from the parts of the design that perform on-chip cryptographic functions. This would permit these vulnerabilities to be identified and reduced to acceptable constraints at design time rather than with a costly chip re-spin after fabrication and test.
[…]The DARPA Common Evaluation Platform (CEP) is a publicly available RISC-V based System-on-a-Chip (SoC). It will be used as a reference design and may have to be extended for the purposes of this program. The reference point for the current state of the art of side channel attack simulation technology will be based on transistor level simulation with SPICE. All the baseline metrics will be based on leakage sources found with SPICE simulation of a meaningful number of traces on the cryptographic block(s) within the CEP.[…]
https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001119S0035-05/listing.html
Firmware Security 