A coreboot convention is in the works for this June in San Francisco area! Excerpt from announcement:

We are going to hold a 4 day coreboot convention in San Francisco, CA, Monday June 13 – Thursday June 16. Google has agreed to host two very nice conference rooms for those 4 days and we are also working to get a block of rooms in a nearby hotel for a reasonable rate.

We plan for two days of talks structured talks, followed by two days of informal discussion and classes. We will have the smaller room open for hacking all four days. We’ll provide flashing equipment and other useful tools; let us know what you need.

There will be a fee for this convention – $250 for corporate employees and $100 for students or individual contributors.  If this is an issue, please let us know on the form and we’ll work with you on a fee waiver.

We have set up an outing on Tuesday night to the Long Now Foundation for the first 40 paid registrations (Long Now has space limits) and we’re working on a visit to a local Hackerspace.

Whether you are part of the Open Source community, working for a silicon vendor supporting coreboot already, or are just interested in getting some hands on experience, our goal is to make this an interesting and valuable meeting for all of us.  You are welcome to present talk proposals and subject areas you think we should cover. We will be having a talk on RISC-V from Andrew Waterman of SiFive, classes by senior members of the community, and discussions on future directions.

Full announcement:
https://www.coreboot.org/pipermail/coreboot/2016-March/081010.html
http://goo.gl/forms/f8uqHHFL2S.
https://www.coreboot.org/Coreboot_conference_San_Francisco_2016

The coreboot project posted their regular project status update. In the last two week period, there have been: 105 commits by 25 authors, adding 13K and removing 3K lines of code. There were updates for multiple boards and chipsets, including Intel Galileo board and Quark chip, Intel Sandy Bridge/Ivy Bridge, Intel Skylake, Intel Bay Trail, Intel Apollo Lake, ARM ARM7 QEMU board, QEMU POWER8, and RISC-V. There were also updates to ARM Trusted Firmware and Verified Boot. Excerpting the announcement:

Payloads got some attention during this period, adding a way to include additional modules into the GRUB2 build. An option was added to build and include coreinfo as a ‘secondary’ payload, allowing it to be run from another payload. We also added U-Boot as a coreboot payload. This is currently still just in development, and needs additional work before it will act as a generic payload for all platforms.

We added LZ4 compression to the build with runtime decompression for cbfs. LZ4’s speed should be roughly the same as LZMA, trading a smaller compressed size for slightly slower decompressoin. LZ4’s main advantage is that it requires much less memory to do the decompression, allowing for compression of stages that couldn’t previously be compressed.

The suite of board-status scripts got several updates, fixing timestamp handling for the sanitized path names, handling when the script is run as super-user in a better way, and adding a script that will set up a Ubuntu Live-image to allow users to more easily run the board-status script.

In the build tools and utilities, we had some fixes for the toolchain builder, updating the GDB builds for x86_64 and MIPS. A couple of scripts were also added. One utility downloads and extracts binary blobs from Chrome OS recovery images, and the other new script allow easier testing of POST cards.

It is always hard to excerpt coreboot blog posts, they have a lot of good data which I’ve omitted. Full post:

coreboot changelog Feb 17 – March 1

The coreboot project does regular blog posts on their project status, which is very nice. (By comparison, the UEFI Forum doesn’t do any such status updates of their Tianocore EDK-II codebase. Neither does the U-Boot project, AFAICT. For all 3, you can track their source tree, and for UEFI you can track their occasional spec updates. But coreboot’s status updates make it a lot easier to see what is happening with the project, without reading source deltas and sifting through threads of checkin emails.)

Last week, coreboot just released version 4.3. The current blog post mentions that version 4.4 is expected towards the end of April. In the last week, they had 30 authors — including 8 new authors! — with 131 commits. A brief excerpt from their blog post, on board support changes during last week:

“We had significant updates to a number of mainboards and the related chipsets in the past week as well. Intel had a large number of changes for their Braswell SoC and its reference board, Strago, merged this week. These included fixes for GPIOs, clocks, SD cards, and thermal support, as well as FSP integration updates. The Asus kgpe-d16 mainboard, along with the AMD Fam10h-Fam15h processor directory and the SB700 soutbridge had numerous patches to improve stability, fix IRQ routing and APIC identification, and improve ACPI. The winbond w83667hg-a was added to the coreboot codebase for the board as well. The Intel d510mo board had some improvements related to native graphics initialization, GPIOs and ACPI. The gigabyte ga-g41m-es2l and the Intel x4x northbridge code had some general cleanup and improvements to cbmem and memory initialization. We also saw the introduction of the initial framework for the new Intel Apollo Lake SoC. We’ll be seeing many more patches related to Apollo Lake in the coming weeks. Other changes of note included code to initialize the PS/2 aux port, a way to access memory address 0 without GCC “optimizing” it into a crash, and the addition of some documentation from Intel about developing new FSP based boards and chipsets. Finally, the Intel sklrvp Skylake reference board was dropped in favor of using the kunimitsu board.”

Full post:

coreboot changelog Jan 27 – Feb 2