PXE-config: PXE config files for BIOS and UEFI

There’s a new github project for BIOS/UEFI-centric PXE use, called PXE-config:

PXE config files for Legacy BIOS and UEFI netboot installs; also contains kickstart files for automated CentOS, Fedora, etc. installs. This repo contains various config files including PXE boot menu config files & kickstart files for unattended installs over PXE boot. It does not contain /etc/dnsmasq.conf, however, which contains PXE server settings for dhcp, tftp boot, and detecting client architectures (Legacy BIOS vs UEFI). dnsmasq.conf can be found in my jun-dotfiles repo on github.

https://github.com/gojun077/pxe-config

LUV/BITS/CHIPSEC ported from x64 to x86!!

Get ready to test your Intel x86 systems!

Megha Dey of Intel submitted an 8-part patch to LUV that enables it to build on x86.

LUV has been useful for 64-bit x64 systems, and now is getting useful for 32-bit x86 systems!

Including 32-bit versions of BITS and CHIPSEC!

Is this the first time that pre-compiled binaries of CHIPSEC for x86 systems have been available? Not sure. Anyway, if you build from source you can start now, otherwise, look for the LUV-live binary download site to start having 32- and 64-bit versions, hopefully

Excerpt from part 0 of the patch:

[PATCH 0/8] Build and run LUV on 32 bit platforms

Currently LUV can be built only for 64 bit target platforms. This patchset contains patches which make sure that LUV can be compiled and run on both 32 as well as 64 bit target platforms. This required reworking of the PE header checks, adding call wrappers used by the shim bootloader to store and restore context, making sure chainloader.c compiled for 32 bit systems, adding support to ensure correct direct directory structure for 32 bit case and removing bugs in chipsec so that it could build without any erros on 32 bit systems. Also, the bits recipe is updated to build the grub EFI image only for target builds.This patchset addresses the following issue:
https://github.com/01org/luv-yocto/issues/57

grub: chainloader: shim: rework PE header checks
grub: shim: Add call wrappers for 32 bit systems
grub: shim: compile chainloader.c for 32bit system
luv : Correct directory structure for 32 bit case
luv: Add the ARCH parameter to chipsec Makefile
luv: chipsec : compile for 32 bit systems
bits: only build grub EFI image for target builds
bits: grub: specify location of images and modules for mkimage

More information:

https://lists.01.org/mailman/listinfo/luv

SwiftOnSecurity on Windows/UEFI security

http://decentsecurity.com/#/securing-your-computer/

There’s a new guide to securing Windows systems. I enjoyed it because step 2 of the steps are firmware-centric, excerpted below, view the original doc, the excerpted formatting is a bit mangled, sorry.

I wish the advice mentioned using CHIPSEC to do security tests to see if system came from OEM with unfixable security flaws, and to use CHIPSEC or other tools — perhaps via LUV-live or directly — to save  a NIST SP-147-style ‘golden image’ of your ROM, doing periodic offline/forensic examination of your ROM images with CHIPSEC, UEFI Firmware Parser, and other tools. (I have no input as to the non-firmware Windows-centric input in the list.)

1.) Update BIOS
For best compatibility and security you should update your computer’s BIOS. A modern BIOS (really UEFI) is a full operating system that runs below and at the same time as Windows, and it needs patches too. People who built computers in the early 2000’s will tell you BIOS updates are risky, and they were, but not anymore. They deliver fixes, features, and security updates you won’t hear about on the news. Even new computers/motherboards need updates. If you’re starting from scratch, do the BIOS update after installing Windows 10. You can find the BIOS update tool on your manufacturer’s driver page for your computer model. You will need to reboot for it to take effect. If you have a Surface, BIOS updates are delivered through Windows Update.

3.) Configure BIOS
This is important and is something nobody talks about. From the boot of your computer, press the setup hotkey. It may be F1, F2, F8, F10, Del, or something else to get into SETUP mode. In the BIOS: Set a setup password. Make it simple, this is only to prevent malicious modification by someone in front of the computer or by a program trying to corrupt it. Change boot to/prioritize UEFI. Disable everything except UEFI DVD, UEFI HDD, and USB UEFI if you plan on using a USB stick to install Windows. Enable the TPM (if available) and SecureBoot (if available) options. This is super important. Disable 1394 (FireWire) and ExpressCard/PCMCIA (if you’re on a laptop) as a layer to further mitigate DMA attacks. This isn’t as important anymore, but if you don’t use them you might as well turn it off. If you want, and if the computer offers it, you can enable a System and HDD password. We will be using BitLocker to protect the disk, but this is an extra layer you can add if you want. I don’t. If you don’t use webcam or microphone, you may be able to turn them off in the BIOS. Save settings and shut down.

The Linux Foundation has some UEFI-centric, Linux-centric desktop advice, which has some overlaps in security methods to the above UEFI-centric, Windows-centric desktop advice:

Linux Foundation IT Security Policies: firmware guidance

The Crypto Party Handbook also has some related advice, for security/privacy-minded use. The Secure Desktop mailing list is the center of the universe for this, where the handful of Linux distributions that focus on secure/privacy as their main features, hang out. If you care about a secure OS, you should be using one of theirs, not an OS where security is not their primary concern.

https://github.com/cryptoparty/handbook

https://secure-os.org/pipermail/desktops/2015-October/000000.html
https://secure-os.org/desktops/charter/

[I need to find some similar security hardening checklist for ChomeOS-based, coreboot-based systems, instead of Windows-based UEFI/BIOS-based systems,  talking about ensuring TPM on x86/x64, using coreboot with Verified Boot, specifics on how to best adopt those keys, like how Nikolaj shows us how to adopt UEFI Secure Boot keys, and others show how to use MOK. Any tips appreciated, please leave a Comment (see left) or send email (see above right). Thanks.]

Wikipedia’s BIOS security roadmap

You’d think that with a blog called ‘firmware security’, I’d know about the ‘Wikipedia BIOS feature comparison’ page. But I did not, sad. 😦  The other day I was wishing someone would create a comparision of BIOS implementations and their security features. Luckily, Kevin O’Conner of the SeaBIOS project was kind enough to point this out to me, when I was looking for a SeaBIOS security roadmap:

https://en.wikipedia.org/wiki/BIOS_features_comparison

I’ve been learning more about SeaBIOS, and am impressed with it’s features. I wonder why some Linux OEMs still ship closed-source BIOS systems from IBVs? Given their audience demographic, you’d think they’d be using Linux-based coreboot, and on x86/x64 systems using SeaBIOS. They could be using coreboot Verified Boot + SeaBIOS’s TPM support for a much more secure than they are today. If you’re buying a System76 or ThinkPenguin or other Linux-centric site, ask them what firmware solution they’re giving you.

Intel Security white paper on hardware/firmware threat predictions

McAfee Labs
2016 Threats Predictions
Intel Security: A five-year look ahead
http://www.mcafee.com/us/mcafee-labs.aspx

Twenty-one thought leaders from Intel Security collaborated to produce this look ahead at how the cybersecurity marketplace and actors are likely to evolve. […]

There are two sections in the document that focus on hardware/fimware security, search for the “Security on Silicon” and “Hardware” sections. A few brief experts:

We currently see only miniscule amounts of malware that target hardware or firmware vulnerabilities, but that is going to change during the next five years. We expect to see many groups leveraging newly discovered techniques, sharing what they know as they try to build effective attacks. Much of this will trickle down, from advanced nation-state intelligence and defense agencies, through big organized crime syndicates, and into broader use. Hardware and firmware protections such as secure boot, trusted execution environments, tamper protection, cryptographic acceleration, active memory protection, and immutable device identity make it more difficult for these attacks to gain a foothold, as well as easier to detect and correct them.

System firmware-based attacks pose a critical risk when coupled with the cloud or with cloud service providers. In 2015, the Intel ATR team demonstrated how to gain access to adjacent virtual machines through multiple vectors, including firmware rootkits or simple misconfigurations. Threats similar to the S3 Boot Script attack can be adapted for in-the-wild attacks. In many cases, it is just a matter of exploiting simple misconfigurations in UEFI or BIOS.

Going forward, we must be hyperaware of the system components below the operation system and how those components can be exploited or leveraged for attack. Available controls for under the operating system attacks include tools like CHIPSEC, and technologies like Intel’s Kernel Guard Technology (iKGT) and Intel BIOS Guard.

I wish that last paragraph mentioned ITL’s Stateless Laptop as one of the solutions.

Hmm, Why are there only BIOS and UEFI attacks mentioned? Where are the coreboot and U-Boot attacks? Are all listed firmware attacks against legacy BIOS systems and UEFI systems, not coreboot or U-Boot attacks? Intel spends resources on both UEFI as well as coreboot, so it seems strange to only see UEFI mentioned in their security. U-Boot also supports Intel these days, apparently without Intel’s involvement. So I’d hope to see a bit of coverage of both coreboot and prehaps a bit of U-Boot.

Is this because firmware attacks are being focused on Windows systems, not Chrome systems, due to marketshare numbers or expertise of attackers/researchers? I recall seeing some news recently claiming that Chrome PCs now outnumber Windows PCs.

Maybe because CHIPSEC only only targets Intel x86/x64 BIOS/UEFI systems, not coreboot/U-Boot systems, or ChromeOS systems, or ARM/AMD/MIPS/Itanium/other architectures, and if CHIPSEC is the only modern firmware vulnerability analysis tool, then lack of tools keeps these other systems’ security profiles dark? Why is AMD not porting CHIPSEC to AMD64, as well as the other handful of x86-compatible vendors?

Why is ARM not porting CHIPSEC to AArch32, only AArch64, and what is status of port, it was mentioned months ago but no status on final port. Once CHIPSEC’s C/asm/Perl userland and C/asm kernel HAL are ported to new arch, and Intel-centric stuff is ifdef’ed out, CHIPSEC still needs new chip-centric security tests added, and I don’t see anyone from ARM/Linaro doing this, so their port will be a gutted empty CHISPEC, not useful without new tests. Where is the ARM report mentioning the lack of CHIPSEC is a huge issue to enterprises ability to protect ARM systems?

Maybe ChromeOS + coreboot’s Verified Boot results in more secure systems than UEFI? Windows systems are UEFI and optional closed-source IBV-based BIOS, if Legacy Mode present. Chrome systems are coreboot and open-source SeaBIOS-based BIOS.

I’m glad Intel provides this kind of white papers. I wish AMD and ARM and other architecture vendors would also offer similar reports. I really wish there was some research on this from a neutral vendor, not a not a chip vendor, so we could see balanced coverage of Intel, AMD, ARM, OpenPOWER, and other systems, and their firmware, covered, including peripheral security (PCIe, NVMe, Thunderbolt, USB, etc. Doesn’t NIST have a hardware/firmware group? I wish they generated a HW/FW periodic security report. It could have the perspective to scope discussion to include trusting closed-source blobs, resident -vs- nonresident firmware solutions and their attack vectors, comparison’s of silicon and firmware (eg, Verified -vs- Secure boot) solutions, and most importantly not just solutions from a single vendor.

Why no ExitRunTimeServices() for UEFI?

The other week, at the 3rd RISC-V Workshop, there were 2 firmware presentations, coreboot and UEFI, pitching their solution for the new RISC-V chip.

One point mentioned in the coreboot presentation that seems worth raising here on a firmware security blog: the distinction between firmware that fully exits -vs- firmware that stays resident while the operating system runs. An interesting way to frame it.

Click to access Tues1345%20riscvcoreboot.pdf

Starting with the IBM PC’s BIOS, Intel systems have had firmware that runs in the background. The OS or an ap would issue a BIOS (or DOS) interrupt, and the BIOS responded to low-level interrupts, like Int 13h for disk, 10h for video, etc. On original PCs, IHVs extended BIOS via Option ROMs via the same extensibility method that IBM PC-DOS ‘services’ (TSRs, ‘terminate and stay resident’) used: hook an interrupt and replace it with yours. So, BIOS is kind of a ‘terminate and stay resident’ firmware.

UEFI uses the same model, presuming firmware to be present in background for OS to call, the resident portion are called UEFI RunTime Services. Once the operating system initializes, it calls UEFI’s ExitBootServices() function, which terminate most — but not all — of UEFI, discarding the init code and only keeping the runtime service code.

http://wiki.phoenix.com/wiki/index.php/EFI_BOOT_SERVICES#ExitBootServices.28.29

Coreboot — and U-Boot — initialize the hardware, but do not stay resident. However, on Intel systems, use of a BIOS payload in coreboot, eg, SeaBIOS, will result in that BIOS payload staying resident, responding to BIOS interrupts that the OS (or an app) may call.

So, the resident -vs- nonresident firmware seems to be tied to Intel -vs- non-Intel: coreboot on ARM for example has no SeaBIOS payload, and RISC-V likey won’t use an Intel-centric BIOS payload.

As the coreboot presentation points out, the resident firmware is an additional attack vector, UEFI has a larger surface than coreboot — or U-Boot — due to UEFI Runtime Services. UEFI currently only  has the option to terminate Boot Time Services — via ExitBootServices(). I wonder if UEFI could have an additional mode, with an ExitRuntimeServices(), that could make UEFI competitive with coreboot/U-Boot w/r/t attack surface? That could be interesting.

SeaBIOS gets TPM2 security

BIOS was designed in the era of the initial IBM PC, running IBM PC-DOS — when DOS meant Disk Operating System not Denial of Service — back when there was no security in any hardware, firmware, or software designs. 🙂 As  UEFI documentation likes to mention, BIOS has no security, unlike UEFI (well, at least v2, EFI v1 had much less security). But SeaBIOS, the open source BIOS implementation, has had TPMv1 support for BIOS (and ACPI) since 2011, and today it just got TPMv2 support! It appears that initial TPMv1 support was added to SeaBIOS in 2011 by Stefan Berger of IBM, including TPM support for ACPI; excerpt from his patch email:


The following set of patches add TPM and Trusted Computing support to SeaBIOS. In particular the patches add:

– a TPM driver for the Qemu’s TPM TIS emulation (not yet in Qemu git)
– ACPI support for the TPM device (SSDT table)
– ACPI support for measurement logging (TCPA table)
– Support for initialzation of the TPM
– Support for the TCG BIOS extensions (1ah handler [ah = 0xbb]) (used by trusted grub; http://trousers.sourceforge.net/grub.html)
– Static Root of Trusted for Measurement (SRTM) support
– Support for S3 resume (sends command to TPM upon resume)
– TPM-specific menu for controlling aspects of the TPM
– [An optional test suite for the TIS interface]

All implementations necessarily follow specifications.

When all patches are applied the following services are available
– SSDT ACPI table for TPM support
– initialization of the TPM upon VM start and S3 resume
– Static root of trust for measurements (SRTM) that measures (some) data of SeaBIOS in TCPA ACPI table
– 1ah interrupt handler offering APIs for measuring and sending commands to the TPM (trusted grub uses them)
– User menu for controlling aspects of the state of the TPM

Full message:
http://www.seabios.org/pipermail/seabios/2011-April/001609.html
https://lists.gnu.org/archive/html/qemu-devel/2011-08/msg03835.html

Steven has an article on the QEMU wiki on SeaBIOS TPMv1 support. And Stephan has a SeaBIOS-TPM project on Github, I’m unclear how this relates to SeaBIOS source tree:
http://wiki.qemu.org/Features/TPM
https://github.com/stefanberger/seabios-tpm

So, that was the old 2011 TPMv1 news, that I am catching up to…. Today, Stephan has a new TPM2 patch for SeaBIOS, excerpt of announcement:

This series of patches adds TPM 2 support to SeaBIOS in the way previously proposed. TPM 2 support also changes the log entry format, which I have not addressed at all so far, and would append to the end of the series.

  tpm: Extend TPM TIS with TPM 2 support.
  tpm: Factor out tpm_extend
  tpm: Prepare code for TPM 2 functions
  tpm: Implement tpm2_startup and tpm2_s3_resume
  tpm: Implement tpm2_set_timeouts
  tpm: Implement tpm2_prepboot
  tpm: Implement tpm2_extend
  tpm: Implement tpm2_menu
  tpm: Implement TPM 2’s set_failure

Full message:
http://www.seabios.org/mailman/listinfo/seabios

Also search the recent checkins for other interesting TPM checkins, eg, Physical Presence API, etc.

I asked on the SeaBIOS list if there was a security roadmap for me to point to, and what consumer devices have TPM support; Kevin O’Connor replied, mentioning the addition of TPMv2, and:

I’m not aware of any new consumer devices shipping with the support, and I understand that KVM/QEMU have had TPM support for some time already.

I think some Google Chromebooks come with coreboot-based TPM-enabled SeaBIOS, and TPM is used to store developer mode state instead of CMOS. I haven’t found canon spec in ChromeOS site, but there are a few online references such as this:
https://news.ycombinator.com/item?id=9185719

I’m not aware of any new consumer devices shipping with the support. If you have a new system, check with the vendor to see if it supports TPM or not. If your BIOS is not SeaBIOS-based, check if it has TPM support; if not, ask the vendor why not.

It would be interesting for a security researcher to compare the BIOS security measures in currently-available consumer devices, SeaBIOS-based and other BIOS codebases. I am not sure how many different BIOS codebases there are, these days. Perhaps AMI and Phoenix have one, and some OEMs? I should research that more. Ralph Brown: help! 🙂

http://www.seabios.org/

BITS: new network-enabled release (and new mailing list)

Burt Triplett of Intel has announced the version 2070 release of BITS (BIOS Implementation Test Suite). The main new feature is network support, but also includes new UEFI and ACPI and Python features, better command line features, and other new features. I’ve just excerpted the first paragraph of the networking-centric portion of the announcement below, there are a lot of implementation caveats to read. See the full announcement for the list of features and bugfixes.

Note that there is also a new BITS mailing list, see below URL for ‘first post’ message in the archives:

BITS on EFI now supports TCP networking, using the Python socket module and various modules built atop it.  On EFI systems that provide `EFI_IP4_CONFIG_PROTOCOL` and `EFI_TCP4_SERVICE_BINDING_PROTOCOL`, we implement a `_socket` module in Python with support for TCP sockets over IPv4.  We then include Python’s higher-level socket module that runs on top of `_socket`.

https://lists.01.org/mailman/listinfo/bits
https://lists.01.org/pipermail/bits/2016-January/000000.html
http://biosbits.org/news/bits-2070/
http://biosbits.org/downloads/bits-2070.zip
https://github.com/biosbits/bits

LUV-live 2.0-RC4 released

Ricardo Neri of Intel announced Linux UEFI Validation (LUV) v2.0-rc4 release, with lots of changes, new versions of CHIPSEC, BITS, FWTS, and multiple UEFI improvements in LUV. IMO, one of the most important features it that LUV-live’s CHIPSEC should properly log results now! Excerpts from Ricardo’s announcement:

This release touches many areas. Here are some highlights:

Naresh Bhat implemented changes to build from Linus’ tree when building LUV for ARM. While doing this, he got rid of the leg-kernel recipe. Now the kernel is built from linux-yocto-efi-test for all architectures. Also, he took the opportunity to remove some of the LUV-specific changes we had in the meta layer (i.e., our genericarmv8 machine). It always good to restrict ourselves to the meta-luv layer, unless we plan to upstream to the Yocto Project. Now LUV for aarch64 is built using qemuarm64.

It was reported that CHIPSEC was not running correctly in LUV due to missing configuration files and Python modules. This release includes a major rework of CHIPSEC integration into LUV. It ran correctly on all the systems in which we tested. Also, we bumped to v1.2.2; the CHIPSEC latest release.

This release includes new functionality to build BITS from its source rather than just deploying its binaries. BITS is a challenging piece of software when it comes to integration into a bitbake recipe. The build process was broken into several steps. This work help for future work to customize BITS for other CPU architectures and netboot.

The UEFI specification v2.5 includes a Properties Table for the memory map. Under this feature, it is possible to split into separate memory sections the code and data regions of the PE/COFF image. Unfortunately, kernels previous to v4.3 crash if this features is enabled. We have backported a fix pushed to Linux v4.3. We will be bumping the kernel for x86 to 4.3 in our next release.

The EFI stub feature in the kernel allows to run the kernel as an EFI application. Also, it allows the kernel to parse the memory map directly from the firmware rather than taking the map from the bootloader. This is clearly advantageous in case of bugs in the bootloader.

Now that LUV support storing the results of multiple bots, it may happen that disk runs out of space. Gayatri Kammela made updates to increase the size of the results partition and issue a warning when available space runs below 2MB.

Finally, keeping up with the latest changes in the Yocto Project has paid off handsomely. This release is based on Jethro, the latest version of the Yocto Project. Rebasing to this new version as done with very little effort. In the LUV tree you can find the jethro and jethro-next branches; the bases of this release. The fido and fido-next branches are still maintained.

We have bumped the following test suite versions:

 *FTWS is now V15.12.00
 *CHIPSEC is now v1.2.2
 *BITS is 2005

Time to update your LUV-live images! It is a Release Candidate, so please help the LUV team by testing it out and pointing out any issues on the LUV mailing list. This version of CHIPSEC includes VMM tests, so time to test LUV-luv in your virtual machines, not just on bare-metal boxes.

Many people contributed to this release, including: Ricardo Neri, Naresh Bhat, Darren Bilby, Megha Dey, Gayatri Kammela, John Loucaides, Sai Praneeth Prakhya, and Thiebaud Weksteen. It was nice to see the LUV and CHIPSEC teams work together in this release!

More information:
https://lists.01.org/pipermail/luv/2015-December/000745.html
https://download.01.org/linux-uefi-validation/v2.0/luv-live-v2.0-rc4.tar.bz2
https://download.01.org/linux-uefi-validation/v2.0/sha256_sums.asc

https://01.org/linux-uefi-validation/

Determining Windows partition information

Patrik Suzzi has an article on GPT partitions, and how to determine if you have MBR or GPT:

The article is written for Windows users, and has lots of screenshots, looks to be informative!

http://www.multibooters.com/guides/determine-if-hard-drive-is-mbr-or-gpt.html

 

SeaBIOS 1.9.0 released

Kevin O’Connor announced the release of SeaBIOS version 1.9.0 today, on the SeaBIOS, QEMU-devel, and coreboot mailing lists. New in this release:

* The default boot menu key is now the ESC key (instead of F12)
* Initial support for Trusted Platform Module (TPM) hardware and BIOS calls
* Initial support for chain loading SeaBIOS from Grub (via multiboot support)
* Initial support for booting from SD cards on real hardware
* virtio 1.0 device support
* The build will no longer include the build hostname or build time on “clean” builds.  This makes the build binaries more “reproducible”.
* Basic support for running SeaBIOS on Baytrail Chromebooks
* SeaVGABIOS: improved support for old versions of x86emu (the “leal” instruction is now emulated)
* Several bug fixes and code cleanups

TPM support sounds interesting! And remember, if F12 no longer works, try ESC…

More information:
http://seabios.org/Releases
http://seabios.org/Download
http://www.seabios.org/mailman/listinfo/seabios

CHIPSEC 1.2.2 released!

After nearly a quarter without an update, CHIPSEC 1.2.2 has been released!!

This release includes multiple new VMM tests — including new fuzzers — hinted at DEF CON and elsewhere, a VENOM test, some S3 tests, support for more Intel CPUs,  as well as a bunch of new/updated features:

NEW modules:
 * tools.vmm.cpuid_fuzz to test CPUID instruction emulation by VMMs
 * tools.vmm.iofuzz to test port I/O emulation by VMMs
 * tools.vmm.msr_fuzz to test CPU Model Specific Registers (MSR) emulation by VMMs
 * tools.vmm.pcie_fuzz to test PCIe device memory-mapped I/O (MMIO) and I/O ranges emulation by VMMs
 * tools.vmm.pcie_overlap_fuzz to test handling of overlapping PCIe device MMIO ranges by VMMs
 * tools.vmm.venom to test for VENOM vulnerability

Updated modules:
 * tools.smm.smm_ptr to perform exhaustive fuzzing of SMI handler for insufficient input validation pointer vulnerabilities
 * smm_dma to remove TSEGMB 8MB alignment check and to use XML “controls”. Please recheck failures in smm_dma.py with the new version.
 * common.bios_smi, common.spi_lock, and common.bios_wp to use XML “controls”
 * common.uefi.s3bootscript which automatically tests protections of UEFI S3 Resume Boot Script table
 * tools.uefi.s3script_modify which allows further manual testing of protections of UEFI S3 Resume Boot Script table

NEW functionality:
 * hal.cpu component to access x86 CPU functionality. Removed hal.cr which merged to hal.cpu
 * hipsec_util cpu utility, removed chipsec_util cr
 * S3 boot script opcodes encoding functionality in hal.uefi_platform
 * hal.iommu, cfg/iommu.xml and chipsec_util iommu to access IOMMU/VT-d hardware
 * chipsec_util io list to list predefined I/O BARs
 * support for Broadwell, Skylake, IvyTown, Jaketown and Haswell Server CPU families
 * ability to define I/O BARs in XML configuration using register attriute similarly to MMIO BARs
 * UEFI firmware volume assembling functionality in hal.uefi
 * Implemented alloc_phys_mem in EFI helper

See the full readme on the github page, which also includes short lists of bugfixes and known-issues:

https://github.com/chipsec/chipsec

If you haven’t been following current security research by Intel’s ATR team, who produces CHIPSEC, watch this video to see why you need to run this new version of CHIPSEC on any machine — after reading CHIPSEC’s warning.txt first — that runs a VMM:

[Hopefully we’ll see Intel LUV team add this release to their project, including LUV-live, soon. There has been a recent patch to LUV that may fix CHIPSEC’s usage in LUV-live, a second important reason to update your LUV-live images.]

LegbaCore adds BIOS/SMM training to OpenSecurityTraining.Info!

They’ve added a 2-day training course on BIOS/SMM, “Advanced x86: Introduction to BIOS & SMM”! The BIOS researchers at MITRE — and half of them now at LebaCore — are one of the main pioneers of BIOS research, and this is one of ther main training sessions. Wow!

“Around 2011, the trustworthy system measurement research project that Xeno Kovah was running at MITRE decided to start digging deeper than the Windows kernel and rootkit detection, to try and detect malicious software at the BIOS level. Xeno & Corey Kallenberg continued to work on Kernel, while team member John Butterworth was tasked with starting to learn about BIOS in parallel. John’s work led to the “BIOS Chronomancy” work (published at both BlackHat and ACM CCS), porting the team’s existing Timing-Based Attestation system from the kernel level down to the BIOS. Xeno then asked John to start making an open source training class to capture his knowledge, the same way that Xeno & Corey had captured their past knowledge on the project and uploaded it to OST. John created a 2 day Intro BIOS class and got it public released from MITRE. The intention originally was that it would cover all basics of BIOS which would be applicable to both legacy BIOS, CoreBoot, or UEFI-based systems. And then it was expected there would be a follow on class digging deeper into the specifics of UEFI. Unfortunately time prohibited the creation of that 2nd 2 days of classes focusing on UEFI, so you can see that some minimal UEFI content was eventually shoehorned into this class, though frequently there isn’t enough time to get to it within 2 days. It is our hope that this Introductory BIOS & SMM class will help demystify how x86 systems work at the low levels, so that people can better understand the BIOS/SMM/SecureBoot vulnerabilities described in the team’s work while at MITRE, and later after Xeno & Corey founded LegbaCore. With this knowledge in hand, hopefully students can fully appreciate and explain to others why it is so critical that BIOS patch management be performed by organizations, to eliminate the vulnerabilities that lurk at this level.

http://opensecuritytraining.info/IntroBIOS.html

VMware UEFI updates

Three tweets from William Lam of VMware, with more information about new features (and one limitation) of UEFI, including a useful VMware UEFI article:

Excerpt from article:

For those of you who may not know, UEFI is meant to eventually replace the legacy BIOS firmware. There are many benefits with using UEFI over BIOS, a recent article that does a good job of explaining the differences can be found here. In doing some research and pinging a few of our ESXi experts internally, I found that UEFI PXE boot support is actually possible with ESXi 6.0. Not only is it possible to PXE boot/install ESXi 6.x using UEFI, but the changes in the EFI boot image are also backwards compatible, which means you could potentially PXE boot/install an older release of ESXi.

http://www.virtuallyghetto.com/2015/10/support-for-uefi-pxe-boot-introduced-in-esxi-6-0.html

 

MMS2015: Terrell and Martin on UEFI

Mike Terrell and Troy Martin are giving a talk at the Midwest Management Summit (MMS) on transitioning Windows systems from BIOS to UEFI.

Making the switch from BIOS to UEFI

The Unified Extensible Firmware Interface (UEFI) is the next generation interface between the operating systems and the platform firmware.  UEFI replaces the legacy Basic Input/Output System (BIOS) firmware that has been around since the beginning of personal computers.  Although UEFI has been around for several years, manufacturers have provided support for legacy BIOS by the means of a Compatibility Support Module (CSM).  This allows support for booting from MBR-partitioned disks.  The downside to this old school booting method is that it is vulnerable to root kits and other intelligent types of malware that inserts itself into the booting process. In this session, you will learn the differences of BIOS and UEFI, the benefits of UEFI and Windows 10 security benefits that are only available when running UEFI.  How to use Configuration Manager to inventory systems that are running UEFI (as well as those that are not).  Also, you will learn about the common pitfalls when making the switch from BIOS to UEFI, how to avoid them, and how zero touch OSD is actually possible when making the switch.

http://mmsmoa.com/
http://mms2015.sched.org/event/a6243319bb0dcd3c631fda78c2763480

BIOS, MBR, and the 0x87C00 mystery

Binni Shah tweeted about a BIOS blog post by Masahiko Sakamoto:

Excerpt of initial post, with all the questions, and none of the answers:

Why BIOS loads MBR into 0x7C00 in x86? The mysteries arround “0x7C00” in x86 architecture bios bootloader? Do you know “0x7C00”, a magic number, in x86 assembler programming ? “0x7C00” is the memory address which BIOS loads MBR (Master Boot Record, a first sector in hdd/fdd) into. OS or bootloader developer must assume that their assembler codes are loaded and start from 0x7C00. But…1st, you may wonder. “I read all of Intel x86(32bit) programmers manual, but did not found the magic number 0x7C00.” Yes. 0x7C00 is NOT related to x86 CPU. It’s natural that you couldn’t find out it in cpu specifications from intel. Then, you wonder, “Who decided it ?” You may wonder: “0x7C00 is 32KiB – 1024B at decimal number. What’s this number means ?” Anyone decided it. But, why he/she decided such a halfway address? Hum…There’re TWO questions (mysteries) arround the magic number “0x7C00”. Who decided “0x7C00”? What “0x7C00 = 32KiB – 1024B” means? Okay, let’s dive into the secret of BIOS for “IBM PC 5150”, ancestor of modern x86(32bit) PCs, with me…!!

Full post:

http://www.glamenv-septzen.net/en/view/6

FWTS updated

Ivan Hu of Canonical has announced the release of FWTS (FirmWare TestSuite), to 5.09.00. FWTS is a set of command line tools for Ubuntu-based and related Linux systems. It also includes a curses-based interface frontend, which is also the default UI to FWTS-live. FWTS is also included in LUV, the Linux UEFI Validation distribution, but it may be a few days until this latest release has been updated in LUV-live. The release features many bugfixes, as well as some new updates/features, including:

* Update ACPICA to version 20150717
* SMBios 3.0.0 tests supported
* acpi: add _CR3 test
* acpi: add _MTL test
* acpi: add _RST test
* acpi: add _PRR test
* dmicheck: SMBIOS 3.0.0 test

For more information, see the full announcement on the fwts-announce mailling list, and see the full changelog, /usr/share/doc/fwts/changelog.Debian.gz in the source tarball.

https://launchpad.net/ubuntu/+source/fwts
http://fwts.ubuntu.com/release/fwts-V15.09.00.tar.gz
https://launchpad.net/~firmware-testing-team/+archive/ubuntu/ppa-fwts-stable
https://wiki.ubuntu.com/FirmwareTestSuite/ReleaseNotes/15.09.00

UEFITool 0.21.0 released

Nikolaj Schlej has released  UEFITool v0.21.0.

Features improved Skylake support, among other things:
– added support for new Intel descriptor type, based on [this](http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1f7fd720c81755144423f2d4062c39cc651adc0a) coreboot commit, thanks to lordkag for issue #32
– solved a bug with incorrect volume free space item placement during volume replace, now works as expected
– solved an issue with incorrect Aptio capsule parsing introduced in 0.20.8

https://github.com/LongSoft/UEFITool
https://firmwaresecurity.com/tag/uefitool/

Bootloader article by .Bx

.Bx has a new article on boot loaders:

As a teaser here’s the first paragraph:

Welcome neighbors. In this blog I will be publishing notes I have taken on UEFI, BIOS, bootloading, ELF, and other technical topics that interest me and seem to lack documentation or explanation. I will also be keeping a list of UEFI, bootloading, and other resources I have found useful on my resources page. The rest of this post will be a whirlwind toure of bootloading and thus fairly introductory, so if you are already familiar with the world of bootloaders you might as well move on and read something else (although I would like to encourage you to look at the section where I propose new general bootloader terminology). In case you want to stick around for the full blog post I will be discussing: my motivations behind studying bootloading, bootloader terminology, how to navigate the plethora of bootloader implementations, specifications that relate to bootloading, BIOS, UEFI, and how they came to be, and how to write a simple boot sector.

Full post:

http://www.cs.dartmouth.edu/~bx/blog/2015/09/03/a-toure-of-bootloading.html